參數(shù)資料
型號： AD9954YSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 37/40頁
文件大?。?/td> 0K
描述： IC DDS DAC 14BIT 1.8V 48-TQFP
產品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝： 1
分辨率（位）： 14 b
主 fclk： 400MHz
調節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應商設備封裝： 48-TQFP 裸露焊盤（7x7）
包裝： 托盤
產品目錄頁面： 552 (CN2011-ZH PDF)
配用： AD9954/PCBZ-ND - BOARD EVAL FOR 9954
AD9954
Rev. B | Page 6 of 40
Parameter
Temp
Test
Level
Min
Typ
Max
Unit
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
25°C
I
1.25
V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
25°C
I
0.6
V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
25°C
I
2.2
V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
25°C
I
0.8
V
Logic 1 Current
25°C
V
3
12
μA
Logic 0 Current
25°C
V
12
μA
Input Capacitance
25°C
V
2
pF
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
25°C
I
1.35
V
Logic 0 Voltage
25°C
I
0.4
V
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
25°C
I
2.8
V
Logic 0 Voltage
25°C
I
0.4
V
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode (Comparator Off )
25°C
I
162
171
mW
With RAM or Linear Sweep Enabled
25°C
I
175
190
mW
With Comparator Enabled
25°C
I
180
190
mW
With RAM and Comparator Enabled
25°C
I
198
220
mW
Rapid Power-Down Mode
25°C
I
150
160
mW
Full-Sleep Mode
25°C
I
20
27
mW
SYNCHRONIZATION FUNCTION4
Maximum Sync Clock Rate (DVDD_I/O = 1.8 V)
25°C
VI
62.5
MHz
Maximum Sync Clock Rate (DVDD_I/O = 3.3 V)
25°C
VI
100
MHz
SYNC_CLK Alignment Resolution5
25°C
V
±1
SYSCLK
cycles
1 Represents the cycle-to-cycle residual jitter from the comparator alone.
2 Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The primary limiting factor is the settling time of the PLL
multiplier in the reference circuitry. The wake-up time assumes there is no capacitor on DAC BP and that the recommended PLL loop filter values are used.
3 SYSCLK cycle refers to the clock frequency used on-chip to drive the DDS core. This is equal to the frequency of the reference source times the value of the PLL-based
reference clock multiplier.
4 SYNC_CLK = SYSCLK rate. Be sure the high speed sync enable bit, CFR2<11>, is programmed appropriately.
5 This parameter indicates that the digital synchronization feature cannot compensate for phase delays (timing skew) between system clock rising edges. If the system
clock edges are aligned, the synchronization function should not increase the skew between the two edges.
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相關代理商/技術參數(shù)
參數(shù)描述
AD9954YSVZ 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48
AD9954YSVZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
AD9954YSVZ-REEL7 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9954YSVZ-REEL71 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
AD9955KS6 制造商:AD 功能描述:*
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