參數(shù)資料
型號(hào): AD9954YSVZ
廠商: Analog Devices Inc
文件頁數(shù): 4/40頁
文件大小: 0K
描述: IC DDS DAC 14BIT 1.8V 48-TQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 400MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
配用: AD9954/PCBZ-ND - BOARD EVAL FOR 9954
AD9954
Rev. B | Page 12 of 40
f (Hz)
L
(f)
(d
B
c/
H
z)
10
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1k
100
100k
1M
10k
10M
03
37
4-
0
28
Figure 17. Residual Phase Noise with fOUT = 159.5 MHz,
fCLK = 400 MSPS; PLL Bypassed (Green), PLL Set to 4× (Red), and
PLL Set to 20× (Blue)
10
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1k
100
100k
10k
1M
03
37
4-
0
29
f (Hz)
L
(f)
(d
B
c/
H
z)
Figure 18. Residual Phase Noise with fOUT = 9.5 MHz, fCLK = 400 MSPS;
PLL Bypassed (Green), PLL Set to 4× (Red), and PLL Set to 20× (Blue)
REF2 200mV 500ns
R2
R1
IT 10.0PS/PT –100PS
M 500PS 20.0GS/S
A CH1
708mV
03
374
-03
0
FALL (R1) = 396.4PS
RISE(R2) = 464.3PS
Figure 19. Comparator Rise and Fall Time at 160 MHz
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