參數(shù)資料
型號(hào)： AD9954YSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/40頁(yè)
文件大?。?/td> 0K
描述： IC DDS DAC 14BIT 1.8V 48-TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 400MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFP 裸露焊盤（7x7）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： AD9954/PCBZ-ND - BOARD EVAL FOR 9954
AD9954
Rev. B | Page 8 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CS
03
37
4-
0
02
31
34
DVDD
33
DGND
32
AGND
29
AVDD
30
COMP_IN
35
PWRDWNCTL
36
RESET
28
COMP_OUT
27
AVDD
26
AGND
25
AVDD
PIN 1
AD9954
TOP VIEW
(Not to Scale)
13
AV
D
14
AG
ND
15
AG
ND
16
AV
D
17
AG
ND
18
AV
D
19
AV
D
20
IOU
T
21
IOU
T
22
AG
ND
23
DAC
BP
24
DAC
_R
SE
T
48
PS
1
47
PS
0
46
OS
K
45
S
Y
NC_CL
K
44
S
Y
NC_I
N
43
DV
DD_I
/O
42
DG
ND
41
SD
IO
40
SC
L
K
39 38
SD
O
37
IOS
Y
N
C
2
DVDD
3
DGND
4
AVDD
7
AGND
6
AVDD
5
AGND
1
I/O UPDATE
8
OSC/REFCLK
9
OSC/REFCLK
10
CRYSTAL OUT
12
LOOP_FILTER
11
CLKMODESELECT
Figure 4. Pin Configuration
Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to
analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V. The DVDD pins (Pin 2 and Pin 34) must be
powered to 1.8 V.
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O
Description
1
I/O UPDATE
I
The rising edge transfers the contents of the internal buffer memory to the I/O registers.
2, 34
DVDD
I
Digital Power Supply Pins (1.8 V).
3, 33, 42
DGND
I
Digital Power Ground Pins.
4, 6, 13, 16,
18, 19, 25,
27, 29
AVDD
I
Analog Power Supply Pins (1.8 V).
5, 7, 14, 15,
17, 22, 26,
32
AGND
I
Analog Power Ground Pins.
8
OSC/REFCLK
I
Oscillator Input/Complementary Reference Clock. When the REFCLK port is operated in
single-ended mode, REFCLK should be decoupled to AVDD with a 0.1 μF capacitor.
9
OSC/REFCLK
I
Oscillator Input/Reference Clock. See Table 5 for details on the OSC/REFCLK operation.
10
CRYSTAL OUT
O
Output of the Oscillator Section.
11
CLKMODESELECT
I
Control Pin for the Oscillator Section (1.8 V logic only). See REFCLK Input section for detailed
instructions.
12
LOOP_FILTER
I
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network varies based on the multiplication value in the PLL loop.
See Table 4 for details.
20
IOUT
O
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
21
IOUT
O
DAC Output. Should be biased through a resistor to AVDD, not AGND.
23
DACBP
I
DAC Band Gap Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.
24
DAC_RSET
I
A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference
current for the DAC. See equation in DAC Output section.
28
COMP_OUT
O
Comparator Output.
30
COMP_IN
I
Comparator Input.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9954YSVZ 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48
AD9954YSVZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
AD9954YSVZ-REEL7 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9954YSVZ-REEL71 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
AD9955KS6 制造商:AD 功能描述:*
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