參數(shù)資料
型號： AD9911BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 22/44頁
文件大?。?/td> 0K
描述： IC DDS 500MSPS DAC 10BIT 56LFCSP
產(chǎn)品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝： 1
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應商設備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
配用： AD9911/PCBZ-ND - BOARD EVAL FOR AD9911
AD9911
Rev. 0 | Page 29 of 44
I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
RELATIONSHIPS
I/O_UPDATE and SYNC_CLK are used together to transfer
data from the I/O buffer to the active registers in the device.
Data in the I/O buffer is inactive.
SYNC_CLK is a rising edge active signal. It is derived from
the system clock and a divide-by frequency divider of 4. The
SYNC_CLK is provided externally to synchronize external
hardware to the AD9911 internal clocks.
I/O_UPDATE initiates the start of a buffer transfer. It can be
sent synchronously or asynchronously relative to the
SYNC_CLK.
If the set-up time between these signals is met, then constant
latency (pipeline) to the DAC output exists. For example, if
repetitive changes to phase offset via the SPI port is desired, the
latency of those changes to the DAC output is constant,
otherwise a time uncertainty of one SYNC_CLK period will be
present.
The I/O UPDATE is sampled on the rising edge of the
SYNC_CLK. Therefore, I/O_UPDATE must have a minimum
pulse width greater than one SYNC_CLK period.
The timing diagram shown in Figure 47 depicts when data in
the I/O buffer is transferred to the active registers.
The I/O UPDATE is set up and held around the rising edge of
SYNC_CLK and has zero hold time and 4.8 ns setup time.
SYNC_CLK
SYSCLK
AB
NN
N – 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
N
N + 1
N + 2
+ 1
I/O UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
05
78
5-
0
44
Figure 47. I/O_UPDATE Timing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9911BCPZ-REEL7 功能描述:IC DDS 500MSPS DAC 10BIT 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9912 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC
AD9912/PCBZ 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS
AD9912A/PCBZ 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板
AD9912ABCPZ 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
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