參數(shù)資料
型號： AD9911BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 18/44頁
文件大小： 0K
描述： IC DDS 500MSPS DAC 10BIT 56LFCSP
產(chǎn)品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝： 1
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
配用： AD9911/PCBZ-ND - BOARD EVAL FOR AD9911
AD9911
Rev. 0 | Page 25 of 44
sweep is then complete and the output held constant in
frequency. See Figure 43 for the linear sweep circuitry.
Figure 45 depicts a frequency sweep with no-dwell mode
disabled. In this mode, the output follows the state of the profile
pin. A phase or amplitude sweep works in the same manner
with fewer bits.
LINEAR SWEEP NO DWELL MODE
To enable linear sweep no dwell mode, set CFR <15>. The rising
sweep is started by setting the profile input pin to 1. The
frequency, phase or amplitude continues to sweep up at the rate
set by the rising sweep ramp rate and the resolution set by the
rising delta tuning word, until it reaches E0. The output then
reverts to the S0 and stalls until high is detected on the
profile pin.
Figure 44 demonstrates the no-dwell mode. The points labeled
A indicate where a rising edge is detected on the profile pin.
Points labeled B indicate at which points where the AD9911 has
determined that the output has reached E0 and reverts to S0.
The falling ramp rate register and the falling delta word are
unused in this mode.
RATE TIME
LOAD CONTROL
LOGIC
LIMIT LOGIC TO
KEEP SWEEP BETWEEN
S0 AND E0
RAMP RATE TIMER:
8-BIT LOADABLE DOWN COUNTER
ACCUMULATOR RESET
LOGIC
0
1
MUX
0
1
MUX
0
1
MUX
PROFILE PIN
0
1
8
MUX
0
1
MUX
FDW
RDW
FSRR
RSRR
0
N
PROFILE PIN
Z–1
CTW1
SWEEP ACCUMULATOR
SWEEP ADDER
CTW0
05
78
5-
0
41
Figure 43. Linear Sweep Block Circuitry
FTW0
SINGLE–TONE
MODE
FTW1
AA
A
B
BB
fOUT
TIME
PS<1> = 1 PS<1> = 0
PS<1> = 0
PS<1> = 1
PS<1> = 0
05
78
5-
04
2
Figure 44. Linear Sweep Mode Enabled—No Dwell Bit Set
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