- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10978 > AD9911BCPZ (Analog Devices Inc)IC DDS 500MSPS DAC 10BIT 56LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9911BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 500MSPS DAC 10BIT 56LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 配用： | AD9911/PCBZ-ND - BOARD EVAL FOR AD9911 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9911
Rev. 0 | Page 21 of 44
Table 4.
CLK_MODE_SEL Pin 24
FR1 <22:18> PLL, Bits = M
Oscillator Enabled
System Clock
(fSYSCLK)
Min/Max Frequency
Range (MHz)
High = 1.8 V Logic
4 ≤ M ≤ 20
Yes
fSYSCLK = fOSC × M
100 < fSYSCLK < 500
High = 1.8 V Logic
M < 4 or M > 20
Yes
fSYSCLK = fOSC
20 < fSYSCLK < 30
Low
4 ≤ M ≤ 20
No
fSYSCLK = fREF CLK × M
100 < fSYSCLK < 500
Low
M < 4 or M > 20
No
fSYSCLK = fREF CLK
0 < fSYSCLK < 500
Reference Clock Input Circuitry
The reference clock input circuitry has two modes of operation.
The first mode (logic low) configures the circuitry as an input
buffer. In this mode, the reference clock must be ac-coupled to
the input due to internal dc biasing. This mode supports either
differential or single-ended configurations. If single-ended
mode is desired, the complementary reference clock input
(Pin 23) should be decoupled to AVDD or AGND via a 0.1 μF
capacitor. The following three figures exemplify common
reference clock configurations for the AD9911.
1:1
BALUN
REF_CLK
PIN 23
REFERENCE
CLOCK
SOURCE
REF_CLK
PIN 22
25
0.1F
05
78
5-
0
37
25
Figure 38. Typical Reference Clock Configuration for Sine Wave Source
The reference clock inputs can also support an LVPECL or
PECL driver as the reference clock source.
REF_CLK
PIN 23
REF_CLK
PIN 22
0.1F
LVPECL/
PECL
DRIVER
TERMINATION
05
78
5-
03
8
Figure 39. Typical Reference Clock Configuration for LVPECL/PECL Source
For external crystal operation, both clock inputs must be dc-
coupled via the crystal leads and bypassed. Figure 40 shows the
configuration when a crystal is used.
REF_CLK
PIN 23
25MHz
XTAL
REF_CLK
PIN 22
39pF
057
85
-03
9
Figure 40. Crystal Configuration for Reference Clock Source
SCALABLE DAC REFERENCE CURRENT CONTROL
MODE
Set the full-scale output current using bits CFR <9:8>, as shown
in Table 5.
Table 5.
CFR <9:8>
LSB Current State
1
Full-scale
0
1
Half-scale
1
0
Quarter-scale
0
Eighth-scale
POWER-DOWN FUNCTIONS
The AD9911 supports pin-controlled power-down plus numer-
ous software selectable power-down modes. Software controlled
power-down allows the input clock circuitry, DAC, and the
digital logic (for the primary and auxiliary DDS cores) to be
individually powered.
When the PWR_DWN_CTL input pin is high, the AD9911
enters power-down mode based on the FR1 <6> bit. When the
PWR_DWN_CTL input pin is low, the individual power-down
bits (CFR <7:4>) control the power-down modes of operation.
See the Control Register Descriptions section for further details.
SHIFT KEYING MODULATION
The AD9911 can perform 2-/4-/8- or 16-level modulation of
frequency, phase, or amplitude (FSK, PSK, ASK) by applying
data to the profile pins. SYNC_CLK must be enabled when
performing FSK, PSK, or ASK, while the auxiliary DDS cores
must be disabled. Digital power down (CSR Bit <7>) of the
auxiliary channels is recommended.
In addition, the AD9911 has the ability to ramp up or ramp
down the output amplitude before, during, or after a
modulation (FSK, PSK only) sequence. This is accomplished by
using the 10-bit output scalar. Profile pins or SDIO_1:3 pins can
be configured to initiate the ramp up/ramp down (RU/RD)
operation. See the Output Amplitude Control section for
further details.
In modulation mode, a set of control bits (CFR<23:22>)
determines the type (frequency, phase, or amplitude) of
modulation. The primary channel (CH1) has 16 profile
registers. Register Address 0x0A through Register Address 0x18
are profile registers for modulation of frequency, phase, or
amplitude. Register 0x04, Register 0x05, and Register 0x06 are
dedicated registers for frequency, phase, and amplitude,
respectively.
These registers contain the initial frequency, phase offset and
amplitude word. Frequency modulation is 32-bit resolution,
phase modulation is 14 bit, and amplitude is 10 bit. When
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-B11-IY-F4 | CONVERTER MOD DC/DC 12V 50W |
| VE-B11-IY-F1 | CONVERTER MOD DC/DC 12V 50W |
| VE-2WZ-IY-F4 | CONVERTER MOD DC/DC 2V 20W |
| VE-2WZ-IY-F1 | CONVERTER MOD DC/DC 2V 20W |
| VE-2WZ-IX-F2 | CONVERTER MOD DC/DC 2V 30W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9911BCPZ-REEL7 | 功能描述:IC DDS 500MSPS DAC 10BIT 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9912 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| AD9912/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS |
| AD9912A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9912ABCPZ | 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。