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參數(shù)資料
| 型號(hào)： | AD9887AKSZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887
DESCRIPTIONS OF PINS SHARED BETWEEN ANALOG
AND DIGITAL INTERFACES
HSOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of
the video HSYNC. The polarity of this output
can be controlled via a serial bus bit. In analog
interface mode the placement and duration
are variable. In digital interface mode the
placement and duration are set by the graphics
transmitter.
VSOUT
Vertical Sync Output
The separated VSYNC from a composite
signal or a direct pass through of the VSYNC
input. The polarity of this output can be con-
trolled via a serial bus bit. The placement and
duration in all modes is set by the graphics
transmitter.
Serial Port (2-Wire)
SDA
Serial Port Data I/O
SCL
Serial Port Data Clock
A0
Serial Port Address Input 1
A1
Serial Port Address Input 2
For a full description of the 2-wire serial regis-
ter and how it works, refer to the Control
Register section.
Data Outputs
RED A
Data Output, Red Channel, Port A/Even
RED B
Data Output, Red Channel, Port B/Odd
GREEN A
Data Output, Green Channel, Port A/Even
GREEN B
Data Output, Green Channel, Port B/Odd
BLUE A
Data Output, Blue Channel, Port A/Even
BLUE B
Data Output, Blue Channel, Port B/Odd
The main data outputs. Bit 7 is the MSB.
These outputs are shared between the two
interfaces and behave according to which
interface is active. Refer to the sections on the
two interfaces for more information on how
these outputs behave.
Data Clock Outputs
DATACK
Data Output Clock
DATACK
Data Output Clock Complement
Just like the data outputs, the data clock out-
puts are shared between the two interfaces.
They also behave differently depending on
which interface is active. Refer to the sections
on the two interfaces to determine how these
pins behave.
Various
SCDT
Chip Active/Inactive Detect Output
The logic for the SCDT pin is [analog interface
HSYNC detection] OR [digital interface DE
detection]. So, the SCDT pin will switch to
logic LOW under two conditions, when nei-
ther interface is active or when the chip is in
full chip power-down mode. The data outputs
are automatically three-stated when SCDT is
LOW. This pin can be read by a controller in
order to determine periods of inactivity.
SCAN Function
SCANIN
Data Input for SCAN Function
Data can be loaded serially into the 48-bit
SCAN register through this pin, clocking it in
with the SCANCLK pin. It then comes out of
the 48 data outputs in parallel. This function
is useful for loading known data into a graph-
ics controller chip for testing purposes.
SCANOUT
Data Output for SCAN Function
The data in the 48-bit SCAN register can be
read through this pin. Data is read on a FIFO
basis and is clocked via the SCANCLK pin.
SCANCLK
Data Clock for SCAN Function
This pin clocks the data through the SCAN
register. It controls both data input and data
output.
OBSOLETE
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| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
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