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參數(shù)資料
| 型號： | AD9887AKSZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/40頁 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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REV. 0
–26–
AD9887
Table IX. Control Register Map (continued)
Read and
Hex
Write or
Default
Register
Address
Read Only
Bits
Value
Name
Function
0FH
R/
W
7:0
1
*******
PLL and
Bit 7—HSYNC Polarity. Indicates the polarity of incoming HSYNC
Clamp Control
signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
*1******
Bit 6—Coast Polarity. Changes polarity of external COAST signal.
(Logic 0 = Active Low, Logic 1 = Active High.)
**0*****
Bit 5—Clamp Function. Chooses between HSYNC for Clamp signal
or another external signal to be used for clamping. (Logic 0 = HSYNC,
Logic 1 = Clamp.)
***1****
Bit 4—Clamp Polarity. Valid only with external CLAMP signal. (Logic 0 =
Active Low, Logic 1 selects Active High.)
****0***
Bit 3—EXTCLK. Shuts down the PLL and allows the use of an external
clock to drive the part. (Logic 0 = use internal PLL, Logic 1 = bypass-
ing of the internal PLL.)
*****0**
Bit 2—Red Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 120).
******0*
Bit 1—Green Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 111).
*******0
Bit 0—Blue Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 101).
10H
R/
W
7:2
0
*******
Mode
Bit 7—Clk Inv: Data clock output invert. (Logic 0 = Not Inverted,
Control 2
Logic 1 = Inverted.) (Digital Interface Only.)
*0******
Bit 6—Pix Select: Selects either 1 or 2 pixels per clock mode.
(Logic 0 = 1 pixel/clock, Logic 1 = 2 pixels/clock.) (Digital Interface
Only.)
**11****
Bit 5, 4—Output Drive: Selects between high, medium, and low
output drive strength. (Logic 11 or 10 = High, 01 = Medium, and
00 = Low.)
****0***
Bit 3—PDO: High Impedance Outputs. (Logic 0 = Normal, Logic
1 = High Impedance.)
*****1**
Bit 2—Sync Detect (SyncDT) Polarity. This bit sets the polarity
for the SyncDT output pin. (Logic 1 = Active High, Logic 0 =
Active Low.)
11H
RO
7:1
Sync Detect/
Bit 7—Analog Interface Hsync Detect. It is set to Logic 1 if Hsync
Active
is present on the analog interface; otherwise it is set to Logic 0.
Interface
Bit 6—Analog Interface Sync-on-Green Detect. It is set to Logic 1
if sync is present on the green video input; otherwise it is set to 0.
Bit 5—Analog Interface Vsync Detect. It is set to Logic 1 if Vsync
is present on the analog interface; otherwise it is set to Logic 0.
Bit 4—Digital Interface Clock Detect. It is set to Logic 1 if the
clock is present on the digital interface; otherwise it is set to Logic 0.
Bit 3—AI: Active Interface. This bit indicates which interface is
active. (Logic 0 = Analog Interface, Logic 1 = Digital Interface.)
Bit 2—AHS: Active Hsync. This bit indicates which analog HSYNC
is being used. (Logic 0 = HSYNC Input Pin, Logic 1 = HSYNC
from Sync-on-Green.)
Bit 1—AVS: Active Vsync. This bit indicates which analog VSYNC
is being used. (Logic 0 = VSYNC input pin, Logic 1 = VSYNC from
sync separator.)
OBSOLETE
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