參數(shù)資料
型號(hào)： AD9887AKSZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/40頁(yè)
文件大小： 0K
描述： IC INTRFACE ANALOG/DVI 160-MQFP
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 圖形卡，VGA 接口
接口： 模擬和數(shù)字
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-MQFP（28x28）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 788 (CN2011-ZH PDF)
REV. 0
AD9887
–31–
When DEMUX = 0, this bit is ignored as data always
comes out of only Port A.
0E
4
HSYNC Output Polarity
One bit that determines the polarity of the HSYNC out-
put and the SOG output. Table XV shows the effect of
this option. SYNC indicates the logic state of the sync pulse.
Table XV. HSYNC Output Polarity Settings
Setting
SYNC
0
Logic 1 (Positive Polarity)
1
Logic 0 (Negative Polarity)
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
0E
3
VSYNC Output Invert
One bit that inverts the polarity of the VSYNC output.
Table XVI shows the effect of this option.
Table XVI. VSYNC Output Polarity Settings
Setting
VSYNC Output
0
Invert
1
No Invert
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
0F
7
HSYNC Input Polarity
A bit that must be set to indicate the polarity of the HSYNC
signal that is applied to the PLL HSYNC input.
Table XVII. HSYNC Input Polarity Settings
HSPOL
Function
0
Active LOW
1
Active HIGH
Active LOW is the traditional negative-going Hsync pulse.
All timing is based on the leading edge of Hsync, which is
the FALLING edge. The rising edge has no effect.
Active HIGH is inverted from the traditional Hsync, with a
positive-going pulse. This means that timing will be based on
the leading edge of Hsync, which is now the RISING edge.
The device will operate if this bit is set incorrectly, but the
internally generated clamp position, as established by
CLPOS, will not be placed as expected, which may gener-
ate clamping errors.
The power-up default value is HSPOL = 1.
0F
6 COAST Input Polarity
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
Table XVIII. COAST Input Polarity Settings
CSTPOL
Function
0
Active LOW
1
Active HIGH
Active LOW means that the clock generator will ignore Hsync
inputs when COAST is LOW, and continue operating at the
same nominal frequency until COAST goes HIGH.
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue operat-
ing at the same nominal frequency until COAST goes LOW.
This function needs to be used along with the COAST
polarity override bit (Register 14, Bit 1).
The power-up default value is CSTPOL = 1.
0F
5 Clamp Input Signal Source
A bit that determines the source of clamp timing.
Table XIX. Clamp Input Signal Source Settings
EXTCLMP
Function
0
Internally-Generated Clamp
1
Externally-Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by
CLPLACE and CLDUR. The clamp position and dura-
tion is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
0F
4
CLAMP Input Signal Polarity
A bit that determines the polarity of the externally pro-
vided CLAMP signal.
Table XX. CLAMP Input Signal Polarity Settings
EXTCLMP
Function
0
Active LOW
1
Active HIGH
A Logic 0 means that the circuit will clamp when CLAMP
is HIGH, and it will pass the signal to the ADC when
CLAMP is LOW.
A Logic 1 means that the circuit will clamp when CLAMP
is LOW, and it will pass the signal to the ADC when
CLAMP is HIGH.
The power-up default value is CLAMPOL = 1.
0F
3 External Clock Select
A bit that determines the source of the pixel clock.
Table XXI. External Clock Select Settings
EXTCLK
Function
0
Internally Generated Clock
1
Externally Provided Clock Signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
OBSOLETE
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