參數(shù)資料
型號: AD9854/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 52/52頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9854
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: AD9854 Eval Brd Schematic
AD9854 Eval Brd BOM
標(biāo)準(zhǔn)包裝: 1
系列: AgileRF™
主要目的: 計時,直接數(shù)字合成(DDS)
已用 IC / 零件: AD9854
已供物品:
相關(guān)產(chǎn)品: AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP
AD9854
Rev. E | Page 9 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76
71 70 69 68
75 74 73 72
21 22 23 24 25 26 27 28 29 30 31 32 33
1
2
3
4
5
6
7
8
9
10
11
13
12
60
59
58
57
56
55
54
53
52
51
50
49
48
NC = NO CONNECT
AD9854
TOP VIEW
(Not to Scale)
WR
/S
C
L
K
RD
/C
S
DV
DD
DV
DD
DV
DD
DG
ND
DG
ND
DG
ND
F
S
K/
BP
S
K/
HO
L
D
OS
K
AV
D
AV
D
AG
ND
DV
DD
DV
DD
DG
ND
DG
ND
DG
ND
DG
ND
DV
DD
DV
DD
DG
ND
M
A
ST
ER
R
E
SET
S/
P
S
EL
EC
T
RE
F
CL
K
RE
F
CL
K
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
DGND
NC
AVDD
AGND
NC
DAC RSET
DACBP
AVDD
AGND
IOUT2
AVDD
IOUT1
PIN 1
INDICATOR
14
15
16
17
18
20
19
47
46
45
44
43
42
41
A5
A4
A3
A2/IO RESET
A1/SDO
A0/SDIO
I/O UD CLK
AGND
AVDD
VINN
VINP
AGND
64 63 62 61
67 66 65
34 35 36 37 38 39 40
AG
ND
NC
VO
U
T
AV
D
AV
D
AG
ND
AG
ND
AG
ND
AG
ND
AV
D
DI
F
CL
K
E
NAB
L
E
NC
AG
ND
PLL
F
IL
T
E
R
00
63
6-
0
02
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 8
D7 to D0
8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
9, 10, 23, 24, 25,
73, 74, 79, 80
DVDD
Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.
11, 12, 26, 27, 28,
72, 75 to 78
DGND
Connections for the Digital Circuitry Ground Return. Same potential as AGND.
13, 35, 57, 58, 63
NC
No Internal Connection.
14 to 16
A5 to A3
Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0). Used only in parallel programming mode.
17
A2/IO RESET
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when
the serial programming mode is selected, allowing an IO RESET of the serial communication bus
that is unresponsive due to improper programming protocol. Resetting the serial bus in this
manner does not affect previous programming, nor does it invoke the default programming
values listed in Table 8. Active high.
18
A1/SDO
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming
mode. SDO is used in 3-wire serial communication mode when the serial programming mode is
selected.
19
A0/SDIO
Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Bidirectional Serial Data I/O. A0 is used only in parallel programming mode. SDIO
is used in 2-wire serial communication mode.
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