VS = 3.3 V ± 5%, RSE" />
參數(shù)資料
型號(hào)： AD9854/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 45/52頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9854
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： AD9854 Eval Brd Schematic
AD9854 Eval Brd BOM
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
已用 IC / 零件： AD9854
已供物品： 板
相關(guān)產(chǎn)品： AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP
AD9854
Rev. E | Page 5 of 52
SPECIFICATIONS
VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ,
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted.
Table 1.
AD9854ASVZ
AD9854ASTZ
Parameter
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Unit
REFERENCE CLOCK INPUT CHARACTERISTICS1
Internal System Clock Frequency Range
REFCLK Multiplier Enabled
Full
VI
20
300
20
200
MHz
REFCLK Multiplier Disabled
Full
VI
DC
300
DC
200
MHz
External Reference Clock Frequency Range
REFCLK Multiplier Enabled
Full
VI
5
75
5
50
MHz
REFCLK Multiplier Disabled
Full
VI
DC
300
DC
200
MHz
Duty Cycle
25°C
IV
45
50
55
45
50
55
%
Input Capacitance
25°C
IV
3
pF
Input Impedance
25°C
IV
100
kΩ
Differential Mode Common-Mode Voltage Range
Minimum Signal Amplitude2
25°C
IV
400
mV p-p
Common-Mode Range
25°C
IV
1.6
1.75
1.9
1.6
1.75
1.9
V
VIH (Single-Ended Mode)
25°C
IV
2.3
V
VIL (Single-Ended Mode)
25°C
IV
1
V
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed
Full
I
300
200
MSPS
Resolution
25°C
IV
12
Bits
I and Q Full-Scale Output Current
25°C
IV
5
10
20
5
10
20
mA
I and Q DAC DC Gain Imbalance3
25°C
I
0.5
+0.15
+0.5
0.5
+0.15
+0.5
dB
Gain Error
25°C
I
6
+2.25
6
+2.25
% FS
Output Offset
25°C
I
2
μA
Differential Nonlinearity
25°C
I
0.3
1.25
0.3
1.25
LSB
Integral Nonlinearity
25°C
I
0.6
1.66
0.6
1.66
LSB
Output Impedance
25°C
IV
100
kΩ
Voltage Compliance Range
25°C
I
0.5
+1.0
0.5
+1.0
V
DAC DYNAMIC OUTPUT CHARACTERISTICS
I and Q DAC Quadrature Phase Error
25°C
IV
0.2
1
0.2
1
Degrees
DAC Wideband SFDR
1 MHz to 20 MHz AOUT
25°C
V
58
dBc
20 MHz to 40 MHz AOUT
25°C
V
56
dBc
40 MHz to 60 MHz AOUT
25°C
V
52
dBc
60 MHz to 80 MHz AOUT
25°C
V
48
dBc
80 MHz to 100 MHz AOUT
25°C
V
48
dBc
100 MHz to 120 MHz AOUT
25°C
V
48
dBc
DAC Narrow-Band SFDR
10 MHz AOUT (±1 MHz)
25°C
V
83
dBc
10 MHz AOUT (±250 kHz)
25°C
V
83
dBc
10 MHz AOUT (±50 kHz)
25°C
V
91
dBc
41 MHz AOUT (±1 MHz)
25°C
V
82
dBc
41 MHz AOUT (±250 kHz)
25°C
V
84
dBc
41 MHz AOUT (±50 kHz)
25°C
V
89
dBc
119 MHz AOUT (±1 MHz)
25°C
V
71
dBc
119 MHz AOUT (±250 kHz)
25°C
V
77
dBc
119 MHz AOUT (±50 kHz)
25°C
V
83
dBc
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