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參數(shù)資料
| 型號(hào)： | AD9854/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9854 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9854 Eval Brd Schematic AD9854 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9854 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP |
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AD9854
Rev. E | Page 42 of 52
EVALUATION BOARD
An evaluation board package is available for the AD9854 DDS
device. This package consists of a PCB, software, and
documentation to facilitate bench analysis of the device’s
performance. To ensure optimum dynamic performance from
the device, users should familiarize themselves with the operation
and performance capabilities of the AD9854 with the evaluation
board and use the evaluation board as a PCB reference design.
EVALUATION BOARD INSTRUCTIONS
The AD9852/AD9854 Revision E evaluation board includes
either an AD9852ASVZ or AD9854ASVZ IC.
The ASVZ package permits 300 MHz operation by virtue of its
thermally enhanced design. This package has a bottom-side
heat slug that must be soldered to the ground plane of the PCB
directly beneath the IC. In this manner, the evaluation board
PCB ground plane layer extracts heat from the AD9852 or
AD9854 IC package. If device operation is limited to 200 MHz
or less, the ASTZ package can be used without a heat slug in
customer installations over the full temperature range.
Evaluation boards for both the AD9852 and AD9854 are
identical except for the installed IC.
To assist in proper placement of the pin header shorting
jumpers, the instructions refer to direction (left, right, top,
bottom) as well as header pins to be shorted. Pin 1 for each
3-pin header is marked on the PCB corresponding with the
schematic diagram. When following these instructions, position
the PCB so that the PCB text can be read from left to right. The
board is shipped with the pin headers configuring the board as
follows:
REFCLK for the AD9852 or AD9854 is configured as
differential. The differential clock signals are provided by
the MC100LVEL16D differential receiver.
The input clock for the MC100LVEL16D is single ended
via J25. This signal may be 3.3 V CMOS or a 2 V p-p sine
wave capable of driving 50 Ω (R13).
Both DAC outputs from the AD9852 or AD9854 are
routed through the two 120 MHz elliptical LP filters, and
their outputs are connected to J7 (Q, or control DAC) and
J6 (I, or cosine DAC).
The board is set up for software control via the printer port
connector.
The output currents of the DAC are configured for 10 mA.
GENERAL OPERATING INSTRUCTIONS
Load the CD software onto your PC’s hard disk. The current
software (Version 1.72) supports Windows 95, Windows 98,
Windows 2000, Windows NT, and Windows XP.
Connect a printer cable from the PC to the AD9854 evaluation
board printer port connector labeled J11.
Hardware Preparation
with these instructions to become acquainted with the electrical
functioning of the evaluation board.
Attach power wires to the connector labeled TB1 using the
screw-down terminals. This connector is plastic and press-fits
over a 4-pin header soldered to the board. Table 11 lists the
connections to each pin.
Table 11. Power Requirements for DUT Pins1
AVDD 3.3 V
DVDD 3.3 V
VCC 3.3 V
Ground
For all DUT
analog pins
For all DUT
digital pins
For all other
devices
For all
devices
1 DUT = device under test.
Clock Input, J25
Attach REFCLK to the clock input, J25. This is a single-ended
input that is routed to the MC100LVEL16D for conversion to
differential PECL output. This is accomplished by attaching a 2 V
p-p clock or sine wave source to J25. Note that this is a 50 Ω
impedance point set by R13. The input signal is ac-coupled and
then biased to the center-switching threshold of the
MC100LVEL16D. To engage the differential clocking mode of the
AD9854, Pin 2 and Pin 3 (the bottom two pins) of W3 must be
connected with a shorting jumper.
The signal arriving at the AD9854 is called the reference clock.
When engaging the on-chip PLL clock multiplier, this signal is
the reference clock for the PLL and the multiplied PLL output
becomes the system clock. If the PLL clock multiplier is to be
bypassed, the reference clock supplied by the user directly
operates the AD9854 and is therefore the system clock.
Three-State Control
The W9, W11, W12, W13, W14, and W15 switch headers must
be shorted to allow the provided software to control the AD9854
evaluation board via the printer port connector, J11.
Programming
If programming of the AD9854 is not to be provided by the
user’s PC and Analog Devices software, the W9, W11, W12,
W13, W14, and W15 headers should be opened (shorting
jumpers removed). This effectively detaches the PC interface
and allows J10 (the 40-pin header) and J1 to assume control
without bus contention. Input signals on J10 and J1 going to the
AD9854 should be 3.3 V CMOS logic levels.
Low-Pass Filter Testing
The purpose of the 2-pin W7 and W10 headers (associated with
J4 and J5) is to allow the two 50 Ω, 120 MHz filters to be tested
during PCB assembly without interference from other circuitry
attached to the filter inputs. Typically, a shorting jumper is
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