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| 型號： | AD9854/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9854 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9854 Eval Brd Schematic AD9854 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9854 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP |
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AD9854
Rev. E | Page 23 of 52
F1
F2
0
F
RE
Q
UE
NC
Y
MODE
TW1
TW2
FSK DATA
TRIANGLE
BIT
010 (RAMPED FSK)
F1
F2
I/O UD CLK
006
36
-04
0
Figure 40. Effect of Triangle Bit in Ramped FSK Mode
F1
F2
0
F
RE
Q
UE
NC
Y
MODE
TW1
TW2
FSK DATA
F1
F2
000 (DEFAULT)
0
010 (RAMPED FSK)
I/O UD CLK
00
63
6-
0
41
Figure 41. Effect of Premature Ramped FSK Data
Figure 41 shows that premature toggling causes the ramp to
immediately reverse itself and proceed at the same rate and
resolution until the original frequency is reached.
The control register contains a triangle bit at Parallel Register
Address 1F hex. Setting this bit high in Mode 010 causes an
automatic ramp-up and ramp-down between F1 and F2 to
occur without toggling Pin 29, as shown in Figure 40. The logic
state of Pin 29 has no effect once the triangle bit is set high. This
function uses the ramp rate clock time period and the step size
of the delta frequency word to form a continuously sweeping
linear ramp from F1 to F2 and back to F1 with equal dwell
times at every frequency. Use this function to automatically
sweep between any two frequencies from dc to Nyquist.
In the ramped FSK mode with the triangle bit set high, an
automatic frequency sweep begins at either F1 or F2, according
to the logic level on Pin 29 (FSK input pin) when the triangle
bit’s rising edge occurs (Figure 42). If the FSK data bit is high
instead of low, F2, rather than F1, is chosen as the start frequency.
Additional flexibility in the ramped FSK mode is provided by
the AD9854’s ability to respond to changes in the 48-bit delta
frequency word and/or the 20-bit ramp rate counter at any time
during the ramping from F1 to F2 or vice versa. To create these
nonlinear frequency changes, it is necessary to combine several
linear ramps with different slopes in a piecewise fashion. This is
done by programming and executing a linear ramp at a rate or
slope and then altering the slope (by changing the ramp rate
clock or delta frequency word, or both). Changes in slope can
be made as often as needed before the destination frequency has
been reached to form the desired nonlinear frequency sweep
response. These piecewise changes can be precisely timed using
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