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| 型號： | AD9854/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9854 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | AD9854 Eval Brd Schematic AD9854 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9854 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP |
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AD9854
Rev. E | Page 29 of 52
USING THE AD9854
INTERNAL AND EXTERNAL UPDATE CLOCK
This update clock function is comprised of a bidirectional
I/O pin (Pin 20) and a programmable 32-bit down-counter. To
program changes that are to be transferred from the I/O buffer
registers to the active core of the DDS, a clock signal (low-to-
high edge) must be externally supplied to Pin 20 or internally
generated by the 32-bit update clock.
When the user provides an external update clock, it is internally
synchronized with the system clock to prevent a partial transfer
of program register information due to a violation of data setup
or hold time. This mode allows the user to completely control when
updated program information becomes effective. The default
mode for the update clock is internal (the internal update clock
control register bit is logic high). To switch to external update
clock mode, the internal update clock control register bit must
be set to logic low. The internal update mode generates automatic,
periodic update pulses at intervals set by the user.
An internally generated update clock can be established by
programming the 32-bit update clock registers (Address 16 hex
to Address 19 hex) and setting the internal update clock control
register bit (Address 1F hex) to logic high. The update clock
down-counter function operates at half the rate of the system
clock (150 MHz maximum) and counts down from a 32-bit
binary value (programmed by the user). When the count
reaches 0, an automatic I/O update of the DDS output or
functions is generated. The update clock is internally and
externally routed to Pin 20 to allow users to synchronize the
programming of update information with the update clock rate.
The time between update pulses is given as
(N + 1)(System Clock Period × 2)
where N is the 32-bit value programmed by the user, and the
allowable range of N is from 1 to (232 1).
The internally generated update pulse that is output from Pin 20
has a fixed high time of eight system clock cycles.
Programming the update clock register to a value less than five
causes the I/O UD CLK pin to remain high. Although the update
clock can function in this state, it cannot be used to indicate when
data is transferring. This is an effect of the minimum high pulse
time when I/O UD CLK functions as an output.
ON/OFF OUTPUT SHAPED KEYING (OSK)
The on/off OSK feature allows the user to control the amplitude vs.
time slope of the I and Q DAC output signals. This function is
used in burst transmissions of digital data to reduce the adverse
spectral impact of short, abrupt bursts of data. Users must first
enable the digital multipliers by setting the OSK EN bit (Control
Register Address 20 hex) to logic high in the control register.
Otherwise, if the OSK EN bit is set low, the digital multipliers
responsible for amplitude control are bypassed and the I and
Q DAC outputs are set to full-scale amplitude.
In addition to setting the OSK EN bit, a second control bit, OSK
INT (also at Address 20 hex), must be set to logic high. Logic high
selects the linear internal control of the output ramp-up or ramp-
down function. A logic low in the OSK INT bit switches control
of the digital multipliers to user-programmable 12-bit registers,
allowing users to dynamically shape the amplitude transition in
practically any fashion. These 12-bit registers, labeled Output
Shape Key I and Output Shape Key Q, are located at Address 21 hex
through Address 24 hex, as listed in Table 8. The maximum output
amplitude is a function of the RSET resistor and is not programmable
when OSK INT is enabled.
ABRUPT ON/OFF KEYING
SHAPED ON/OFF KEYING
ZERO
SCALE
ZERO
SCALE
FULL
SCALE
FULL
SCALE
00636
-049
Figure 49. On/Off Output Shaped Keying
The transition time from zero scale to full scale must also be
programmed. The transition time is a function of two fixed
elements and one variable. The variable element is the program-
mable 8-bit ramp rate counter. This is a down-counter that is
clocked at the system clock rate (300 MHz maximum) and that
generates one pulse whenever the counter reaches 0. This pulse
is routed to a 12-bit counter that increments with each pulse
received. The outputs of the 12-bit counter are connected to the
12-bit digital multiplier. When the digital multiplier has a value
of all 0s at its inputs, the input signal is multiplied by 0, producing
zero scale. When the multiplier has a value of all 1s, the input
signal is multiplied by a value of 4095 or 4096, producing nearly
full scale. There are 4094 remaining fractional multiplier values that
produce output amplitudes scaled according to their binary values.
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