參數(shù)資料
型號: AD9779ABSVZRL
廠商: Analog Devices Inc
文件頁數(shù): 6/56頁
文件大小: 0K
描述: DAC 16BIT 1.0GSPS 100-TQFP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
設計資源: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016)
Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018)
Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019)
Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020)
Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
標準包裝: 1,000
位數(shù): 16
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 300mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 1G
AD9776A/AD9778A/AD9779A
Rev. B | Page 14 of 56
74
VREF
73
IPTAT
72
AGND
69
CSB
70
RESET
71
IRQ
75
I120
68
SCLK
67
SDIO
66
SDO
64
DGND
63
SYNC_O+
62
SYNC_O–
61
DVDD33
60
DVDD18
59
P2D0
58
P2D1
57
P2D2
56
P2D3
55
P2D4
54
DGND
53
DVDD18
52
P2D5
51
P2D6
65
PLL_LOCK
PIN 1
100
AV
DD
33
99
AG
ND
98
AV
DD
33
97
AG
ND
96
AV
DD
33
95
AG
ND
94
AG
ND
93
O
U
T
1_P
92
O
U
T
1_N
91
AG
ND
90
AUX
1_P
89
AUX
1_N
88
AG
ND
87
AUX
2_N
86
AUX
2_P
85
AG
ND
84
O
U
T
2_N
83
O
U
T
2_P
82
AG
ND
81
AG
ND
80
AV
DD
33
79
AG
ND
78
AV
DD
33
77
AG
ND
76
AV
DD
33
26
P1
D
8
27
P1
D
7
28
P1
D
6
29
P1
D
5
30
P1
D
4
31
P1
D
3
32
DG
ND
33
DV
DD18
34
P1
D
2
35
P1
D
1
36
P1
D
0
37
DAT
ACL
K
38
DV
DD33
39
T
X
E
N
ABL
E
/I
Q
S
E
L
E
CT
40
P2D
15
41
P2D
14
42
P2D
13
43
DV
DD18
44
DG
ND
45
P2D
12
46
P2D
11
47
P2D
10
48
P2
D
9
49
P2
D
8
50
P2
D
7
2
CVDD18
3
CGND
4
CGND
7
CGND
6
REFCLK–
5
REFCLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D15
18
P1D14
19
P1D13
20
P1D12
21
P1D11
22
DGND
23
DVDD18
24
P1D10
25
P1D9
11
CGND
AD9779A
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
06
45
2-
0
04
NOTES
1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED
PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR
THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.
Figure 5. AD9779A Pin Configuration
Table 9. AD9779A Pin Function Descriptions
Pin
No.
Mnemonic
Description
Pin
No.
Mnemonic
Description
1
CVDD18
1.8 V Clock Supply.
19
P1D13
Port 1, Data Input D13.
2
CVDD18
1.8 V Clock Supply.
3
CGND
Clock Ground.
4
CGND
Clock Ground.
5
REFCLK+
Differential Clock Input.
6
REFCLK
Differential Clock Input.
7
CGND
Clock Ground.
8
CGND
Clock Ground.
9
CVDD18
1.8 V Clock Supply.
10
CVDD18
1.8 V Clock Supply.
11
CGND
Clock Ground.
12
AGND
Analog Ground.
13
SYNC_I+
Differential Synchronization Input.
14
SYNC_I
Differential Synchronization Input.
15
DGND
Digital Ground.
16
DVDD18
1.8 V Digital Supply.
17
P1D15
Port 1, Data Input D15 (MSB).
18
P1D14
Port 1, Data Input D14.
20
P1D12
Port 1, Data Input D12.
21
P1D11
Port 1, Data Input D11.
22
DGND
Digital Ground.
23
DVDD18
1.8 V Digital Supply.
24
P1D10
Port 1, Data Input D10.
25
P1D9
Port 1, Data Input D9.
26
P1D8
Port 1, Data Input D8.
27
P1D7
Port 1, Data Input D7.
28
P1D6
Port 1, Data Input D6.
29
P1D5
Port 1, Data Input D5.
30
P1D4
Port 1, Data Input D4.
31
P1D3
Port 1, Data Input D3.
32
DGND
Digital Ground.
33
DVDD18
1.8 V Digital Supply.
34
P1D2
Port 1, Data Input D2.
35
P1D1
Port 1, Data Input D1.
36
P1D0
Port 1, Data Input D0 (LSB).
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