參數(shù)資料
型號(hào): AD9779ABSVZRL
廠商: Analog Devices Inc
文件頁數(shù): 34/56頁
文件大小: 0K
描述: DAC 16BIT 1.0GSPS 100-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016)
Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018)
Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019)
Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020)
Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 300mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 1G
AD9776A/AD9778A/AD9779A
Rev. B | Page 4 of 56
FUNCTIONAL BLOCK DIAGRAM
10
CLOCK GENERATION/DISTRIBUTION
DATA
ASSEMBLER
DIGITAL CONTROLLER
SINC^-1
CLOCK
MULTIPLIER
2×/4×/8×
16-BIT
I DAC
REFCLK+
REFCLK–
OUT1_P
OUT1_N
AUX1_P
AUX1_N
AUX2_P
AUX2_N
OUT2_P
OUT2_N
GAIN
16-BIT
Q DAC
SINC^-1
I
LATCH
DELAY
LINE
Q
LATCH
P2D[15:0]
P1D[15:0]
SYNC_O
SYNC_I
DATACLK
n ×
fDAC/8
n = 0, 1, 2 ... 7
POWER-ON
RESET
SD
O
SD
IO
SC
L
K
CS
B
SERIAL
PERIPHERAL
INTERFACE
CO
M
P
L
E
X
M
O
DUL
AT
O
R
E
F
E
RE
NC
E
AND
BI
AS
VREF
I120
DELAY
LINE
AD9779A
0
64
52
-0
01
Figure 2. AD9779A Functional Block Diagram
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