參數(shù)資料
型號(hào)： AD9779ABSVZRL
廠商： Analog Devices Inc
文件頁數(shù)： 20/56頁
文件大?。?/td> 0K
描述： DAC 16BIT 1.0GSPS 100-TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016)
Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018)
Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019)
Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020)
Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 300mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 1G
AD9776A/AD9778A/AD9779A
Rev. B | Page 27 of 56
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and controls the internal state machines. The maximum frequency
of SCLK is 40 MHz. All data input is registered on the rising edge
of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should
stay low during the entire communication cycle.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this
pin can be used as a bidirectional data line. The configuration
of this pin is controlled by Register 0x00, Bit 7. The default is
Logic 0, configuring the SDIO pin as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the device
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the LSB-/MSB-first
register bit (Register 0x00, Bit 6). The default is MSB-first format
(LSB/MSB first = 0).
When MSB-first format is selected (LSB/MSB first = 0), the
instruction and data bit must be written from MSB to LSB.
Multibyte data transfers in MSB-first format start with an
instruction byte that includes the register address of the most
significant data byte. Subsequent data bytes should follow from
high address to low address. In MSB-first mode, the serial port
internal byte address generator decrements for each data byte of
the multibyte communication cycle.
When LSB/MSB first = 1 (LSB first) the instruction and data
bit must be written from LSB to MSB. Multibyte data transfers
in LSB-first format start with an instruction byte that includes
the register address of the least significant data byte, followed by
multiple data bytes. The serial port internal byte address genera-
tor increments for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the data
address written toward 0x00 for multibyte I/O operations if the
MSB-first format is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first format is active.
R/W N1 N0 A4 A3
A2 A1 A0 D7 D6N D5N
D00
D10
D20
D30
D7 D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
06
45
2-
05
0
Figure 53. Serial Register Interface Timing, MSB First
A0 A1 A2 A3 A4
N0 N1 R/W D00 D10 D20
D7N
D6N
D5N
D4N
D00 D10 D20
D7N
D6N
D5N
D4N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
06
45
2-
05
1
Figure 54. Serial Register Interface Timing, LSB First
INSTRUCTION BIT 6
INSTRUCTION BIT 7
CSB
SCLK
SDIO
tDS
tDH
tPWH
tPWL
tSCLK
06
45
2-
05
2
Figure 55. Timing Diagram for 3-Wire Interface Register Write
DATA BIT n – 1
DATA BIT n
CSB
SCLK
SDIO
SDO
tDV
0
64
52
-0
53
Figure 56. Timing Diagram for 3-Wire Interface Register Read
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參數(shù)描述
AD9779A-DPG2-EBZ 功能描述:BOARD EVALUATION FOR AD9779A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9779A-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk
AD9779AMOD-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk
AD9779AXSVZ 制造商:Analog Devices 功能描述:DUAL 16-BIT, 1 GSPS, DIGITAL-TO-ANALOG CONVERTER - Bulk
AD9779BSV 制造商:Analog Devices 功能描述:DAC 2CH INTERPOLATION FLTR 16BIT 100TQFP EP - Bulk
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