參數(shù)資料
型號： AD9600ABCPZ-150
廠商： Analog Devices Inc
文件頁數(shù)： 8/72頁
文件大小： 0K
描述： IC ADC 10BIT 150MSPS 64LFCSP
標準包裝： 1
位數(shù)： 10
采樣率（每秒）： 150M
數(shù)據(jù)接口： 串行，SPI?
轉換器數(shù)目： 2
功率耗散（最大）： 890mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
AD9600
Rev. B | Page 16 of 72
Pin No.
Mnemonic
Type
Description
ADC Fast Detect Outputs
54
FD0+
Output
Channel A/Channel B LVDS Fast Detect Indicator 0 True (see Table 14 for full details).
53
FD0
Output
Channel A/Channel B LVDS Fast Detect Indicator 0 Complement (see Table 14
for details).
56
FD1+
Output
Channel A/Channel B LVDS Fast Detect Indicator 1 True (see Table 14 for details).
55
FD1
Output
Channel A/Channel B LVDS Fast Detect Indicator 1 Complement (see Table 14
for details).
59
FD2+
Output
Channel A/Channel B LVDS Fast Detect Indicator 2 True (see Table 14 for details).
58
FD2
Output
Channel A/Channel B LVDS Fast Detect Indicator 2 Complement (see Table 14
for details).
61
FD3+
Output
Channel A/Channel B LVDS Fast Detect Indicator 3 True (see Table 14 for details).
60
FD3
Output
Channel A/Channel B LVDS Fast Detect Indicator 3 Complement (see Table 14
for details).
Digital Inputs
52
SYNC
Input
Digital Synchronization Pin (Slave Mode Only).
Digital Outputs
9
D0+
Output
Channel A/Channel B LVDS Output Data 0 True.
8
D0
Output
Channel A/Channel B LVDS Output Data 0 Complement.
13
D1+
Output
Channel A/Channel B LVDS Output Data 1 True.
12
D1
Output
Channel A/Channel B LVDS Output Data 1 Complement.
15
D2+
Output
Channel A/Channel B LVDS Output Data 2 True.
14
D2
Output
Channel A/Channel B LVDS Output Data 2 Complement.
17
D3+
Output
Channel A/Channel B LVDS Output Data 3 True.
16
D3
Output
Channel A/Channel B LVDS Output Data 3 Complement.
19
D4+
Output
Channel A/Channel B LVDS Output Data 4 True.
18
D4
Output
Channel A/Channel B LVDS Output Data 4 Complement.
23
D5+
Output
Channel A/Channel B LVDS Output Data 5 True.
22
D5
Output
Channel A/Channel B LVDS Output Data 5 Complement.
26
D6+
Output
Channel A/Channel B LVDS Output Data 6 True.
25
D6
Output
Channel A/Channel B LVDS Output Data 6 Complement.
28
D7+
Output
Channel A/Channel B LVDS Output Data 7 True.
27
D7
Output
Channel A/Channel B LVDS Output Data 7 Complement.
30
D8+
Output
Channel A/Channel B LVDS Output Data 8 True.
29
D8
Output
Channel A/Channel B LVDS Output Data 8 Complement.
32
D9+
Output
Channel A/Channel B LVDS Output Data 9 True.
31
D9
Output
Channel A/Channel B LVDS Output Data 9 Complement.
11
DCO+
Output
Channel A/Channel B LVDS Data Clock Output True.
10
DCO
Output
Channel A/Channel B LVDS Data Clock Output Complement.
SPI Control
48
SCLK/DFS
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
47
SDIO/DCS
I/O
SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode.
51
CSB
Input
SPI Chip Select (Active Low).
Signal Monitor Port
33
SMI SDO/OEB
I/O
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in
External Pin Mode.
35
SMI SDFS
Output
Signal Monitor Serial Data Frame Sync.
34
SMI SCLK/PDWN
I/O
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
Do Not Connect
2 to 7, 62, 63
DNC
N/A
Do Not Connect.
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