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| 型號： | AD9600ABCPZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 150MSPS 64LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 150M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 890mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9600
Rev. B | Page 27 of 72
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 60). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V and therefore offers
several selections for the drive logic voltage.
OPTIONAL
100
0.1F
39k
CMOS
DRIVER
50
CLK–
CLK+
ADC
AD9600
VCC
1k
1k
CLK+
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
06
90
9-
02
7
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (up to 150 MSPS)
100
0.1F
VCC
CMOS
DRIVER
50
CLK–
CLK+
ADC
AD9600
1k
1k
CLK+
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
06
90
9-
0
28
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (up to 150 MSPS)
Input Clock Divider
The AD9600 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD9600 clock divider can be synchronized by using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized either on every SYNC signal
or on only the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows aligning the clock dividers of
multiple devices to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a ±5% tolerance
is required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9600 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling (or falling) edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock
input duty cycles without affecting the performance of the
AD9600. When the SDIO/DCS pin functions as DCS, noise and
distortion performance are nearly flat for a wide range of duty
cycles, as shown in Figure 43.
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 20 MHz
nominally. The loop has a time constant associated with it that
needs to be considered if the clock rate may change dynamically.
This requires a wait time of 1.5 μs to 5 μs after a dynamic clock
frequency increase or decrease before the DCS loop is relocked
to the input signal. During this time, the loop is not locked, the
DCS loop is bypassed, and the internal device timing is dependent
on the duty cycle of the input clock signal. In such applications,
it may be appropriate to disable the duty clock stabilizer. In all
other applications, enabling the DCS circuit is recommended to
maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated as
(
)
J
IN
t
f
SNR
×
π
=
2
log
20
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter. IF undersampling
applications are particularly sensitive to jitter (see Figure 62).
06
90
9-
16
2
65
60
55
50
45
1
10
100
1000
S
N
R
(
d
Bc)
INPUT FREQUENCY (MHz)
3.00ps
0.05ps
0.20ps
0.5ps
1.0ps
1.50ps
2.00ps
2.50ps
MEASURED
Figure 62. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9600.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
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