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參數(shù)資料
| 型號： | AD9600ABCPZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 150MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 150M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 890mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9600
Rev. B | Page 45 of 72
Increase Gain Dwell Time (Register 0x10A and
Register 0x10B)
Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0]
Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8]
These registers are programmed with the dwell time in ADC
clock cycles. The signal must be below the fine lower threshold
value before the increase gain (IG) indicator is asserted.
Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved
Bit 6—DC Correction Freeze
When Bit 6 is set high, the dc correction is not updated to the
signal monitor block; therefore, the block continues to hold the last
dc value that it calculated.
Bits [5:2]—DC Correction Bandwidth
These bits set the averaging time of the power monitor dc
correction function. This 4-bit word sets the bandwidth of the
correction block according to the following equation:
π
×
=
2
_
14
CLK
k
f
BW
Corr
DC
where:
k is the 4-bit value programmed in Register 0x10C, Bits [5:2]
(values between 0 and 13 are valid for k; programming 14 or
15 provides the same result as programming 13).
fCLK is the AD9600 ADC sample rate in hertz.
Bit 1—DC Correction for Signal Path Enable
Setting Bit 1 high causes the output of the dc measurement block to
be summed with the data in the signal path to remove the dc offset
from the signal path.
Bit 0—DC Correction for Signal Monitor Enable
Bit 0 enables the dc correction function in the signal monitor block.
The dc correction is an averaging function that can be used by
the signal monitor to remove dc offset in the signal. Removing
this dc from the measurement allows a more accurate reading.
Signal Monitor DC Value Channel A (Register 0x10D and
Register 0x10E)
Register 0x10D, Bits [7:0]—DC Value Channel A [7:0]
Register 0x10E, Bits [7:6]—Reserved
Register 0x10E, Bits [5:0]—DC Value Channel A [13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel A.
Signal Monitor DC Value Channel B (Register 0x10F and
Register 0x110)
Register 0x10F Bits [7:0]—DC Value Channel B [7:0]
Register 0x110 Bits [7:6]—Reserved
Register 0x110 Bits [5:0]—DC Value Channel B [13:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel B.
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved
Bit 6—RMS/MS Magnitude Output Enable
These bits enable the 20-bit rms or ms magnitude measurement
as output on the SPORT.
Bit 5—Peak Detector Output Enable
Bit 5 enables the 10-bit peak measurement as output on the SPORT.
Bit 4—Threshold Crossing Output Enable
Bit 4 enables the 10-bit threshold measurement as output on
the SPORT.
Bits [3:2]—SPORT SMI SCLK Divide
The values of these bits set the SPORT SMI SCLK divide ratio
from the input clock. A value of 0x01 sets divide by 2 (default),
a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.
Bit 1— SPORT SMI SCLK Sleep
Setting Bit 1 high causes the SMI SCLK to remain low when the
signal monitor block has no data to transfer.
Bit 0—Signal Monitor SPORT Output Enable
When set, Bit 0 enables the SPORT output of the signal monitor
to begin shifting out the result data from the signal monitor block.
Signal Monitor Control (Register 0x112)
Bit 7—Complex Power Calculation Mode Enable
This mode assumes that I data is present on one channel and
Q data is present on the opposite channel. The result reported
is the complex power, measured as
2
Q
I +
Bits [6:4]—Reserved
Bit 3—Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting
Bit 3 high selects ms power measurement mode.
Bits [2:1]—Signal Monitor Mode
Bit 2 and Bit 1 set the mode of the signal monitor for the data
output of Register 0x116 to Register 0x11B. Setting Bit 2 and Bit 1
to 00 selects rms/ms magnitude output, setting these bits to 01
selects peak power output, and setting to 10 or 11 selects threshold
crossing output.
Bit 0—Signal Monitor Enable
Setting Bit 0 high enables the signal monitor block.
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