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參數(shù)資料
| 型號： | AD9600ABCPZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/72頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 150MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 150M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 890mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極 |
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AD9600
Rev. B | Page 44 of 72
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x118
Signal Monitor
Result
Channel A
Register 2
(Global)
Open
Signal Monitor Value Channel A [19:16]
Read only.
0x119
Signal Monitor
Result
Channel B
Register 0
(Global)
Signal Monitor Result Channel B [7:0]
Read only.
0x11A
Signal Monitor
Result
Channel B
Register 1
(Global)
Signal Monitor Result Channel B [15:8]
Read only.
0x11B
Signal Monitor
Result
Channel B
Register 2
(Global)
Open
Signal Monitor Result Channel B [19:16]
Read only.
MEMORY MAP REGISTER DESCRIPTION
For information about functions controlled in Register 0x00 to
Register 0xFF, see Application Note AN-877, Interfacing to High
Speed ADCs via SPI.
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external sync input to the
signal monitor block. The sync signal is passed when both Bit 7
and Bit 0 are high. This is continuous sync mode.
Bits [6:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100 [0]) is high and the
clock divider sync enable bit (Address 0x100 [1]) is high, the
clock divider next sync only bit (Address 0x100 [2]) allows the
clock divider to sync to the first sync pulse it receives and ignore
the rest. The clock divider sync enable bit (Address 0x100 [1])
resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
passed when both Bit 1 and Bit 0 are high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable the sync functions.
Fast Detect Control (Register 0x104)
Bits [7:4]—Reserved
Bits [3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output pins according
to Table 14.
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect output pins. When the fast
detect output pins are disabled, the outputs go into a high
impedance state. In LVDS mode, when the fast detect output
pins are interleaved, the outputs go high-Z only if both channels
are turned off (power-down/standby/output disabled). If only one
channel is turned off (power-down/standby/output disabled), the
fast detect output pins repeat the data of the active channel.
Coarse Upper Threshold (Register 0x105)
Bits [7:3]—Reserved
Bits [2:0]—Coarse Upper Threshold
These bits set the level required to assert the coarse upper
threshold indication (see Table 18).
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0]
Register 0x107, Bits [7:5]—Reserved
Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8]
These registers provide the fine upper limit threshold. This 13-bit
value is compared with the 10-bit magnitude from the ADC
block. If the ADC magnitude exceeds this threshold value, the
F_UT indicator is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0]
Register 0x109, Bits [7:5]—Reserved
Register 0x109, Bits [4:0]—Fine Lower Threshold [12:8]
These registers provide a fine lower limit threshold. This 13-bit
value is compared with the 10-bit magnitude from the ADC
block. If the ADC magnitude is less than this threshold value,
the F_LT indicator is set.
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