參數(shù)資料
型號： AD9146-M5375-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 47/56頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9146 DAC
設(shè)計資源： AD9146-M5375-EBZ Schematic
AD9146-M5375-EBZ Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 1G
數(shù)據(jù)接口： 串行
設(shè)置時間： 20ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9146
Data Sheet
AD9146
Rev. A | Page 51 of 56
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of the
IRQ pin when a single error is detected.
1. Load the following comparison values. (Comparison values
can be chosen arbitrarily; however, choosing values that
require frequent bit toggling provides the most robust test.)
Register 0x68: I0LSB
Register 0x69: I0MSB
Register 0x6A: Q0LSB
Register 0x6B: Q0MSB
Register 0x6C: I1LSB
Register 0x6D: I1MSB
Register 0x6E: Q1LSB
Register 0x6F: Q1MSB
2. Enable the SED error detect flag to assert the IRQ pin.
(Set Register 0x05 to 0x04.)
3. Begin transmitting the input data pattern.
4. Write to Register 0x67 to enable the SED.
(Set Register 0x67 to 0x80.)
5. Clear the SED errors in Register 0x67 and Register 0x07.
When the SED is first turned on, the FRAME signal may
be detected immediately; therefore, the SED failure bit may
be asserted due to the unknown initial FRAME status. For
this reason, the SED compare fail status bit must be cleared
at least once immediately after enabling the SED.
If IRQ is asserted, read Register 0x67 and Register 0x70 through
Register 0x73 to verify that a SED error was detected and to deter-
mine which input bits were in error. The bits in Register 0x70
through Register 0x73 are latched; therefore, the bits indicate
any errors that occurred on those bits throughout the test (not
only the errors that caused the error detected flag to be set).
Enabling the alignment of the I0 sample as described in the
SED Operation section requires the use of the FRAME signal.
The timing diagrams for byte and nibble modes are the same
as during normal operation and are shown in Figure 33 and
Figure 34, respectively.
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