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參數(shù)資料
| 型號： | AD9146-M5375-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9146 DAC |
| 設(shè)計資源： | AD9146-M5375-EBZ Schematic AD9146-M5375-EBZ Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1G |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 20ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9146 |
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Data Sheet
AD9146
Rev. A | Page 43 of 56
DEVICE POWER MANAGEMENT
POWER DISSIPATION
The AD9146 has three supply rails: AVDD33, DVDD18, and
CVDD18.
The AVDD33 supply powers the DAC core circuitry. The power
dissipation of the AVDD33 supply rail is independent of the digital
operating mode and sample rate. The current drawn from the
AVDD33 supply rail is typically 54 mA (188 mW) when the full-
scale current of the I and Q DACs is set to the nominal value of
20 mA. Changing the full-scale current directly affects the supply
current drawn from the AVDD33 rail. For example, if the full-scale
current of the I DAC and the Q DAC is changed to 10 mA, the
AVDD33 supply current drops by 20 mA to 34 mA.
The DVDD18 supply powers all of the digital signal processing
blocks of the device. The serial port I/O pins, the RESET pin,
and the IRQ pin are also supplied from the DVDD18 power
supply. The power consumption from this supply is a function
of which digital blocks are enabled and the frequency at which
the device is operating.
The CVDD18 supply powers the clock receiver and clock distri-
bution circuitry. The power consumption from this supply varies
directly with the operating frequency of the device. CVDD18 also
powers the PLL. The power dissipation of the PLL is typically
80 mA when enabled.
Figure 59 through Figure 61 show the power dissipation of
the AD9146 under a variety of operating conditions. All of the
graphs were taken with data being supplied to both the I and Q
DACs. The power consumption of the device does not vary
significantly with changes in the coarse modulation mode selected
or with the analog output frequency. Figure 59 shows the total
power dissipation. Figure 60 and Figure 61 show the power
dissipation of the DVDD18 and CVDD18 supplies.
Maximum power dissipation can be estimated to be 20% higher
than the typical power dissipation.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
PO
W
ER
D
ISSI
PA
TION
(
W)
fDATA (MSPS)
09691-
100
4× INTERPOLATION
2× INTERPOLATION
Figure 59. Total Power Dissipation vs. fDATA Without PLL and Inverse Sinc
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
fDATA (MSPS)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PO
W
ER
D
ISSI
PA
TION
(
W)
09691-
101
4× INTERPOLATION
2× INTERPOLATION
Figure 60. DVDD18 Power Dissipation vs. fDATA Without Inverse Sinc
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
fDATA (MSPS)
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
PO
W
ER
D
ISSI
PA
TION
(
W)
09691-
102
4× INTERPOLATION
2× INTERPOLATION
Figure 61. CVDD18 Power Dissipation vs. fDATA with PLL Disabled
Tx ENABLE
The Tx enable feature provides additional power management
techniques that can be implemented in system applications. The
TXENABLE pin, when taken to a logic low, stops the trans-
mission of data from the part and clamps the outputs to midscale.
In addition, various portions of the DAC can be powered down
while the pin is held low, depending on the power saving require-
ments of the system and the amount of wake-up time required
when the pin is brought high.
Register 0x02 contains the bit controls to power down these
individual blocks: DAC cores, FIFO, interpolation filters, PLL,
and the internal reference. Depending on the power-down bits
selected, the necessary wake-up time and reprogramming of the
DAC may vary.
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