參數(shù)資料
型號(hào)： AD9146-M5375-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 40/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9146 DAC
設(shè)計(jì)資源： AD9146-M5375-EBZ Schematic
AD9146-M5375-EBZ Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 1G
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 20ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9146
Data Sheet
AD9146
Rev. A | Page 45 of 56
MULTICHIP SYNCHRONIZATION
System demands may require that the outputs of multiple DACs
be synchronized with each other or with a system clock. Systems
that support transmit diversity or beamforming, where multiple
antennas are used to transmit a correlated signal, require multiple
DAC outputs to be phase aligned with each other. Systems with a
time division multiplexing transmit chain may require one or more
DACs to be synchronized with a system-level reference clock.
Multiple devices are considered synchronized to each other when
the state of the clock generation state machines is identical for all
parts, and when time-aligned data is being read from the FIFOs
of all parts simultaneously. Devices are considered synchronized
to a system clock when there is a fixed and known relationship
between the clock generation state machine and the data being
read from the FIFO and a particular clock edge of the system
clock. The AD9146 has provisions for enabling multiple devices
to be synchronized to each other or to a system clock.
The AD9146 supports synchronization in two different modes:
data rate mode and FIFO rate mode. In data rate mode, the input
data rate represents the lowest synchronized clock rate. In FIFO
rate mode, the FIFO rate, which is the data rate divided by the
FIFO depth of 8, represents the lowest rate clock.
The advantage of FIFO rate synchronization is increased time
between the setup and hold time windows for DCI changes
relative to the DACCLK or REFCLK input. When the synchro-
nization state machine is on in data rate mode, the elasticity of
the FIFO is not used to absorb timing variations between the data
source and the DAC, resulting in setup and hold time windows
repeating at the input data rate.
The method chosen for providing the DAC sampling clock directly
affects the synchronization methods available. When the device
clock multiplier is used, only data rate mode is available. When
the DAC sampling clock is sourced directly, both data rate
mode and FIFO rate mode synchronization are available. The
following sections describe the synchronization methods for
enabling both clocking modes and querying the status of the
synchronization logic.
The full synchronization methods described are used to align
multiple dual DACs within one DACCLK cycle. To achieve syn-
chronization within one DACCLK cycle, both the REFCLK and
FRAME signals are required to perform back-end and front-end
alignment. If synchronization does not need to be this accurate,
other options can be used. In data rate mode or in FIFO rate mode,
using soft alignment of the FIFO for multiple DACs synchronizes
the DAC outputs within two data clock cycles (see the Serial Port
Initiated FIFO Reset section). For more information about
synchronization, see the AN-1093 Application Note, “Synchro-
nization of Multiple AD9122 TxDAC+ Converters.”
SYNCHRONIZATION WITH CLOCK MULTIPLICATION
When using the clock multiplier to generate the DAC sample
rate clock, the REFCLK input signal acts as both the reference
clock for the PLL-based clock multiplier and as the synchronization
signal. To synchronize devices, distribute the REFCLK signal
with low skew to all the devices that need to be synchronized.
Skew between the REFCLK signals of the different devices
shows up directly as a timing mismatch at the DAC outputs.
Because two clocks are shared on the same signal, an appropriate
frequency must be chosen for the synchronization and REFCLK
signals. The FRAME and DCI signals can be created in the FPGA
along with the data. A circuit diagram of a typical configuration
is shown in Figure 62.
SYSTEM
CLOCK
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
REFCLKP/
REFCLKN
FRAMEP/
FRAMEN
DCIP/
DCIN
REFCLKP/
REFCLKN
FRAMEP/
FRAMEN
DCIP/
DCIN
IOUT1P/
IOUT1N
IOUT2P/
IOUT2N
FPGA
09691-
069
Figure 62. Typical Circuit Diagram for Synchronizing Devices
outlines the steps required to synchronize multiple devices. The
procedure assumes that the REFCLK signal is applied to all the
devices, and that the PLL of each device is phase locked to it. The
following procedure must be carried out on each individual device.
Procedure for Synchronization When Using the PLL
In the initialization of the AD9146, all the clock signals (DACCLK,
DCI, FRAME, synchronization, and REFCLK) must be present and
stable before the synchronization feature is turned on. Configure
the AD9146 for data rate, periodic synchronization by writing
0xC8 to the sync control register (Register 0x10). Additional
synchronization options are available (see the Additional
Read the sync status register (Register 0x12) to verify that the
sync locked bit (Bit 6) is set high, indicating that the device
achieved back-end synchronization, and that the sync lost bit
(Bit 7) is low. These levels indicate that the clocks are running
with a constant and known phase relative to the synchroniza-
tion signal.
Reset the FIFO by strobing the FRAME signal high for the time
interval required to write two complete input data words. Resetting
the FIFO ensures that the correct data is being read from the FIFO.
This completes the synchronization procedure; all devices should
now be synchronized.
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