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參數(shù)資料
| 型號： | AD9146-M5375-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/56頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9146 DAC |
| 設計資源： | AD9146-M5375-EBZ Schematic AD9146-M5375-EBZ Gerber Files |
| 標準包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1G |
| 數(shù)據(jù)接口： | 串行 |
| 設置時間： | 20ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9146 |
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Data Sheet
AD9146
Rev. A | Page 47 of 56
Reset the FIFO by strobing the FRAME signal high for two
complete DCI periods. Resetting the FIFO ensures that the
correct data is being read from the FIFO of each of the devices
simultaneously.
This completes the synchronization procedure; all devices should
now be synchronized.
To ensure that each DAC is updated with the correct data on
the same CLK edge, two timing relationships must be met on
each DAC.
DCIP/DCIN and D[7:0]P/D[7:0]N must meet the setup
and hold times with respect to the rising edge of DACCLK.
REFCLK must also meet the setup and hold times with
respect to the rising edge of DACCLK.
When these conditions are met, the outputs of the DACs are
updated within one DAC clock cycle of each other. The timing
requirements of the input signals are shown in Figure 65.
DACCLKP(1)/
DACCLKN(1)
DACCLKP(2)/
DACCLKN(2)
REFCLKP(2)/
REFCLKN(2)
DCIP(2)/
DCIN(2)
FRAMEP(2)/
FRAMEN(2)
tSKEW
tSUSYNC
tSDCI
tHDCI
tHSYNC
09
69
1-
0
72
Figure 65. Data Rate Synchronization Signal Timing Requirements,
2× Interpolation
Figure 65 shows the synchronization signal timing with 2×
interpolation; therefore, fDCI = × fCLK. The REFCLK input is
shown to be equal to the data rate. The maximum frequency at
which the device can be resynchronized in data rate mode can
be expressed as
fSYNC_I = fDATA/2N
where N is any non-negative integer.
Generally, for values of N greater than or equal to 3, select the
FIFO rate synchronization mode.
When synchronization is used in data rate mode, the timing
constraint between the DCI and DACCLK must be met accord-
ing to Table 24. In data rate mode, the allowed phase drift between
the DCI and DACCLK is limited to one DCI period. The DCI to
DACCLK timing restriction is required to prevent corruption of
the data transfer when the FIFO is constantly reset. The required
timing between the DCI and DACCLK is shown in Figure 66.
DCI
DACCLK/
REFCLK
tDATA
tHDCI
tSDCI
DATA VALID
WINDOW
tHDCI
tSDCI
0
96
91
-0
43
Figure 66. Timing Diagram for Input Data Port (Data Rate Mode)
Table 24. DCI to DACCLK Setup and Hold Times
DCI Delay
Register 0x16,
Bits[1:0]
Minimum Setup
Time, tSDCI (ns)
Minimum Hold
Time, tHDCI (ns)
Sampling
Interval (ns)
00
0.07
0.82
0.75
01
0.24
1.13
0.89
10
0.39
1.40
1.01
11
0.49
1.55
1.06
FIFO RATE MODE SYNCHRONIZATION
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in FIFO rate mode.
The procedure assumes that the DACCLK and REFCLK signals
are applied to all the devices. The procedure must be carried out
on each individual device.
Procedure for FIFO Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
Configure the AD9146 for FIFO rate, periodic synchronization
by writing 0x88 to the sync control register (Register 0x10). Addi-
tional synchronization options are available (see the Additional
Read the sync locked bit (Register 0x12, Bit 6) to verify that
the device is back-end synchronized. A high level on this bit
indicates that the clocks are running with a constant and known
phase relative to the synchronization signal.
Reset the FIFO by strobing the FRAME signal high for two complete
DCI periods. Resetting the FIFO ensures that the correct data is
being read from the FIFO of each of the devices simultaneously.
This completes the synchronization procedure; all devices should
now be synchronized.
To ensure that each DAC is updated with the correct data on the
same CLK edge, two timing relationships must be met on each DAC.
DCIP/DCIN and D[7:0]P/D[7:0]N must meet the setup
and hold times with respect to the rising edge of DACCLK.
REFCLK must also meet the setup and hold times with
respect to the rising edge of DACCLK.
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