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參數(shù)資料
| 型號： | AD9146-M5375-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9146 DAC |
| 設(shè)計資源： | AD9146-M5375-EBZ Schematic AD9146-M5375-EBZ Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1G |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 20ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9146 |
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Data Sheet
AD9146
Rev. A | Page 37 of 56
DAC INPUT CLOCK CONFIGURATIONS
The AD9146 DAC sampling clock (DACCLK) can be sourced
directly or by clock multiplying. Clock multiplying uses the
on-chip phase-locked loop (PLL), which accepts a reference clock
operating at a submultiple of the desired DACCLK rate, most
commonly the data input frequency. The PLL then multiplies
the reference clock up to the desired DACCLK frequency, which
can then be used to generate all the internal clocks required by
the DAC. The clock multiplier provides a high quality clock that
meets the performance requirements of most applications. Using
the on-chip clock multiplier eliminates the need to generate and
distribute the high speed DACCLK.
The second mode bypasses the clock multiplier circuitry and
allows the DACCLK to be sourced directly to the DAC core.
This mode enables the user to source a very high quality clock
directly to the DAC core. Sourcing the DACCLK directly through
the REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may
be necessary in demanding applications that require the lowest
possible DAC output noise, particularly when directly synthesizing
signals above 150 MHz.
DRIVING THE DACCLK AND REFCLK INPUTS
The differential DACCLK and REFCLK inputs share similar
clock receiver input circuitry. Figure 47 shows a simplified circuit
diagram of the inputs. The on-chip clock receiver has a differential
input impedance of about 10 k. It is self-biased to a common-
mode voltage of about 1.25 V. The inputs can be driven by
direct coupling differential PECL or LVDS drivers. The inputs
can also be ac-coupled if the driving source cannot meet the
input compliance voltage of the receiver.
1.25V
5k
DACCLKP,
REFCLKP
DACCLKN,
REFCLKN
09691-
052
Figure 47. Clock Receiver Input Simplified Equivalent Circuit
The minimum input drive level to either of the clock inputs is
100 mV p-p differential. The optimal performance is achieved
when the clock input signal is between 800 mV p-p differential
and 1.6 V p-p differential. Whether using the on-chip clock
multiplier or sourcing the DACCLK directly, it is necessary that
the input clock signal to the device have low jitter and fast edge
rates to optimize the DAC noise performance.
DIRECT CLOCKING
Direct clocking with a low noise clock produces the lowest noise
spectral density at the DAC outputs. To select the differential
CLK inputs as the source for the DAC sampling clock, set the
PLL enable bit (Register 0x0A, Bit 7) to 0. This powers down
the internal PLL clock multiplier and selects the input from the
DACCLKP and DACCLKN pins as the source for the internal
DAC sampling clock.
The device also has duty cycle correction circuitry and differ-
ential input level correction circuitry. Enabling these circuits can
provide improved performance in some cases. The control bits
for these functions are in Register 0x08 (see Table 11).
CLOCK MULTIPLICATION
The on-chip PLL clock multiplication circuit can be used to gen-
erate the DAC sampling clock from a lower frequency reference
clock. When the PLL enable bit (Register 0x0A, Bit 7) is set to 1,
the clock multiplication circuit generates the DAC sampling clock
from the lower rate REFCLK input. The functional diagram of
the clock multiplier is shown in Figure 48.
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the REFCLK input signal
frequency multiplied by N1 × N0.
fVCO = fREFCLK × (N1 × N0)
The DAC sampling clock frequency, fDACCLK, is equal to
fDACCLK = fREFCLK × N1
The output frequency of the VCO must be chosen to keep fVCO
in the optimal operating range of 1.0 GHz to 2.1 GHz. The
frequency of the reference clock and the values of N1 and N0
must be chosen so that the desired DACCLK frequency can be
synthesized and the VCO output frequency is in the correct range.
DACCLKP/DACCLKN
(PIN 3 AND PIN 4)
ADC
VCO
LOOP
FILTER
REFCLKP/REFCLKN
(PIN 6 AND PIN 7)
REG 0x0E[3:0]
VCO CONTROL
VOLTAGE
REG 0x0D[3:2]
N0
REG 0x0D[1:0]
N1
÷N1
÷N0
REG 0x06[7:6]
PLL LOCK LOST
PLL LOCKED
PHASE
DETECTION
REG 0x0A[7]
PLL ENABLE
REG 0x0D[7:6]
N2
÷N2
DACCLK
PC_CLK
09691-
053
Figure 48. PLL Clock Multiplication Circuit
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