參數(shù)資料
型號(hào)： AD9146-M5375-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9146 DAC
設(shè)計(jì)資源： AD9146-M5375-EBZ Schematic
AD9146-M5375-EBZ Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC+®
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 1G
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 20ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9146
AD9146
Data Sheet
Rev. A | Page 30 of 56
Serial Port Initiated FIFO Reset
A serial port initiated FIFO reset can be issued in any mode and
always results in a relative FIFO reset. To initialize the FIFO data
level through the serial port, Bit 1 of Register 0x18 should be
toggled from 0 to 1 and back. When the write to this register is
complete, the FIFO data level is initialized. When the initializa-
tion is triggered, the next time that the read pointer becomes 0,
the write pointer is set to the value of the FIFO start level variable
(Register 0x17, Bits[2:0]) upon initialization. By default, this
value is 4, but it can be programmed to a value from 0 to 7.
The recommended procedure for a serial port FIFO data level
initialization is as follows:
1.
Program Register 0x17 to 0x05.
2.
Request FIFO level reset by setting Register 0x18, Bit 1, to 1.
3.
Verify that the part acknowledges the request by ensuring
that Register 0x18, Bit 2, is set to 1.
4.
Remove the request by setting Register 0x18, Bit 1, to 0.
5.
Verify that the part drops the acknowledge signal by
ensuring that Register 0x18, Bit 2, is set to 0.
6.
Read back Register 0x19 to verify that the pointer spacing
is set to 3 (0x07) or 4 (0x0F).
7.
If the readback of Register 0x19 shows a pointer spacing
of 2 (0x03), increment Register 0x17 to a spacing of 0x06
and repeat Step 2 through Step 5. Read back Register 0x19
again to verify that the pointer spacing is now set to 3 (0x07).
8.
If the readback of Register 0x19 shows a pointer spacing
of 5 (0x1F) after Step 6, decrement Register 0x17 to a
spacing of 0x04 and repeat Step 2 through Step 5. Read
back Register 0x19 again to verify that the pointer spacing
is now set to 4 (0x0F).
FRAME Initiated Relative FIFO Reset
The primary function of the FRAME input is to indicate to
which DAC the input data is written. Another function of the
FRAME input is to initialize the FIFO data level value. This is
done by asserting the FRAME signal high for at least the time
interval required to load complete data to the I and Q DACs.
This corresponds to four DCI periods in byte mode and eight
DCI periods in nibble mode.
To initiate a relative FIFO reset with the FRAME signal, the device
must be configured in data rate mode (Register 0x10, Bit 6 = 1).
When FRAME is asserted in data rate mode, the write pointer is
set to 4 by default (or to the FIFO start level) the next time that
the read pointer becomes 0 (see Figure 35).
09
69
1-
04
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
FIFO WRITE RESETS
READ
POINTER
FRAME
WRITE
POINTER
Figure 35. FRAME Input vs. Write Pointer Value, Data Rate Mode
FRAME Initiated Absolute FIFO Reset
In FIFO rate synchronization mode, the write pointer of the FIFO
is reset in an absolute manner. The synchronization signal aligns
the internal clocks on the part to a common reference clock so
that the pipeline delay in the digital circuit stays the same during
power cycles. The synchronization signal is sampled by the DAC
clock in the AD9146. The edge of the DAC clock used to sample
the synchronization signal is selected by Bit 3 of Register 0x10.
The FRAME signal is used to reset the FIFO write pointer. In
the FIFO rate synchronization mode, the FIFO write pointer is
reset immediately after the FRAME signal is asserted high for at
least the time interval required to load complete data to the I
and Q DACs. The FIFO write pointer is reset to the value of the
FIFO Phase Offset[2:0] bits in Register 0x17. FIFO rate synchro-
nization is selected by setting Bit 6 of Register 0x10 to 0.
READ
POINTER
WRITE
POINTER
SYNC
FRAME
FIFO READ RESET
FIFO WRITE
RESET
FIFO PHASE OFFSET[2:0]
REG 0x17[2:0] = 101
01
3
2
1
0
7
6
5
4
3
2
3
2
1
0
7
6
5
66
5
47
09
69
1
-04
1
Figure 36. FRAME Input vs. Write Pointer Value, FIFO Rate Mode
Monitoring the FIFO Status
The FIFO initialization and status can be read from Register 0x18.
This register provides information about the FIFO status and
whether the initialization was successful. The MSB of Register 0x18
is a FIFO warning flag that can optionally trigger a device IRQ.
This flag indicates that the FIFO is close to emptying (FIFO
level is 1) or overflowing (FIFO level is 7). In this case, data
may soon be corrupted, and action should be taken.
The FIFO data level can be read from Register 0x19 at any time.
The serial port reported FIFO data level is denoted as a 7-bit
thermometer code (Base 1 code) of the write counter state relative
to the absolute read counter being at 0. The optimum FIFO data
level of 4 is therefore reported as a value of 00001111 in the status
register.
Note that, depending on the timing relationship between the DCI
and the main DACCLK, the FIFO level value can be off by a ±1
count; that is, the readback of Register 0x19 can be 00011111 in
the case of a +1 count and 00000111 in the case of a 1 count.
Therefore, it is important to keep the difference between the
read and write pointers to a value of at least 2.
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