參數(shù)資料
型號(hào): AD7851ANZ
廠商: Analog Devices Inc
文件頁數(shù): 22/36頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SRL 333KSPS 24-DIP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 15
位數(shù): 14
采樣率(每秒): 333k
數(shù)據(jù)接口: 8051,QSPI?,串行,SPI? µP
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 89.25mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)偽差分,單極;1 個(gè)偽差分,雙極
–29–
REV. B
AD7851
SERIAL
INTERFACE
MODE
?
NO
YES
TRANSFER
DATA
DURING
CONVERSION
?
APPLY
SYNC (IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON DOUT PIN,
AND WRITE ALL 0s ON DIN PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR WAIT FOR BUSY BIT = 0
APPLY
SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL
REGISTER SETTING
CONVST BIT TO 1, READ CURRENT
CONVERSION RESULT ON DOUT PIN
2, 3
INITIATE
CONVERSION
IN
SOFTWARE
?
WAIT APPROXIMATELY 200ns
AFTER
CONVST RISING EDGE
APPLY
SYNC (IF REQUIRED),
SCLK, READ PREVIOUS CONVERSION
RESULT ON DOUT PIN,
AND WRITE ALL 0s ON DIN PIN
NO
YES
TRANSFER
DATA DURING
CONVERSION
APPLY
SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL
REGISTER SETTING
CONVST BIT TO 1, READ PREVIOUS
CONVERSION RESULT ON DOUT PIN (SEE NOTE)
YES
NO
NOTE: WHEN USING THE SOFTWARE CONVERSION START AND
TRANSFERRING DATA DURING CONVERSION, THE USER MUST ENSURE
THE CONTROL REGISTER WRITE OPERATION EXTENDS BEYOND THE
FALLING EDGE OF BUSY. THE FALLING EDGE OF BUSY RESETS THE
CONVST BIT TO 0 AND ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED
TO 1 TO START THE NEXT CONVERSION.
START
POWER ON, APPLY CLKIN SIGNAL,
WAIT FOR AUTOMATIC CALIBRATION
PULSE
CONVST PIN
WAIT FOR BUSY SIGNAL TO GO
LOW OR WAIT FOR BUSY BIT = 0
Figure 41. Flowchart for Setting Up, Reading, and Writing in Interface Modes 2 and 3
Writing to the AD7851
For accessing the on-chip registers, it is necessary to write to the
part. To enable Serial Interface Mode 1, the user must also write
to the part. Figures 41, 42, and 43 shows how to configure the
AD7851 for each of the different serial interface modes. The
continuous loops on all diagrams indicate the sequence for more
than one conversion. The options of using a hardware (pulsing
the
CONVST pin) or software (setting the CONVST bit to 1)
conversion start, and reading/writing during or after conversion
are shown in Figures 41 and 42. If the
CONVST pin is never
used, then it should be tied to DVDD permanently. Where refer-
ence is made to the BUSY bit equal to a Logic 0, to indicate the
end of conversion, the user in this case would poll the BUSY bit
in the status register.
Interface Modes 2 and 3 Configuration
Figure 41 shows the flowchart for configuring the part in Inter-
face Modes 2 and 3. For these interface modes, the read and
write operations take place simultaneously via the serial port.
Writing all 0s ensures that no valid data is written to any of the
registers. When using the software conversion start and transfer-
ring data during conversion, the Figure 41 note must be obeyed.
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