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參數(shù)資料
| 型號： | AD7192BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CH SD 24-TSSOP |
| 設(shè)計(jì)資源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極；4 個偽差分，單極；4 個偽差分，雙極 |
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AD7192
Rev. A | Page 31 of 40
Continuous Read
Rather than write to the communications register each time a
conversion is complete to access the data, the AD7192 can be
configured so that the conversions are placed on the DOUT/
RDY line automatically. By writing 01011100 to the communi-
cations register, the user need only apply the appropriate
number of SCLK cycles to the ADC, and the conversion word
is automatically placed on the DOUT/RDY line when a
conversion is complete. The ADC should be configured for
continuous conversion mode.
When DOUT/RDY goes low to indicate the end of a conversion,
sufficient SCLK cycles must be applied to the ADC; the data
conversion is then placed on the DOUT/RDY line. When the
conversion is read, DOUT/RDY returns high until the next
conversion is available. In this mode, the data can be read only
once. Also, the user must ensure that the data-word is read
before the next conversion is complete. If the user has not read
the conversion before the completion of the next conversion,
or if insufficient serial clocks are applied to the AD7192 to
read the word, the serial output register is reset when the next
conversion is complete, and the new conversion is placed in
the output serial register.
To exit the continuous read mode, the Instruction 01011000
must be written to the communications register while the
RDY pin is low. While in the continuous read mode, the ADC
monitors activity on the DIN line so that it can receive the
instruction to exit the continuous read mode. Additionally, a
reset occurs if 40 consecutive 1s are seen on DIN. Therefore,
DIN should be held low in continuous read mode until an
instruction is to be written to the device.
When several channels are enabled, the ADC continuously
steps through the enabled channels and performs one con-
version on each channel each time that it is selected. DOUT/
RDY pulses low when a conversion is available. When the user
applies sufficient SCLK pulses, the data is automatically placed
on the DOUT/RDY pin. If the DAT_STA bit in the mode
register is set to 1, the contents of the status register are output
along with the conversion. The status register indicates the
channel to which the conversion corresponds.
DIN
SCLK
DOUT/RDY
CS
0x5C
DATA
0
782
2-
0
23
Figure 31. Continuous Read
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