DVDD
參數(shù)資料
型號(hào)： AD7192BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/41頁(yè)
文件大小： 0K
描述： IC ADC 24BIT 2CH SD 24-TSSOP
設(shè)計(jì)資源： Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119)
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 4.8k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極；2 個(gè)差分，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
AD7192
Rev. A | Page 25 of 40
ADC CIRCUIT INFORMATION
MCLK1 MCLK2
P0/REFIN2(–) P1/REFIN2(+)
DVDD DGND
5V
AIN1
IN+
IN–
OUT–
OUT+
AIN2
AIN3
AIN4
AINCOM
REFIN1(–)
BPDSW
AGND
AD7192
REFIN1(+)
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
TEMP
SENSOR
CLOCK
CIRCUITRY
AVDD
AGND
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
AVDD
AGND
Σ-Δ
ADC
PGA
MUX
0
78
22
-01
2
Figure 18. Basic Connection Diagram
OVERVIEW
The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ
modulator, a buffer, PGA, and on-chip digital filtering intended
for the measurement of wide dynamic range signals such as
those in pressure transducers, weigh scales, and strain gage
applications.
The part can be configured to have two differential inputs or
four pseudo differential inputs that can be buffered or unbuffered.
Figure 18 shows the basic connections required to operate the part.
FILTER, OUTPUT DATA RATE, AND SETTLING TIME
A Σ-Δ ADC consists of a modulator followed by a digital filter.
The AD7192 has two filter options: a sinc3 filter and a sinc4
filter. The filter is selected using the SINC3 bit in the mode
register. When the SINC3 bit is set to 0 (default value), the sinc4
filter is selected. The sinc3 filter is selected when the SINC3 bit is
set to 1.
At low output data rates (<1 kHz), the noise-free resolution is
comparable for the two filter types. However, at the higher
update rates, the sinc4 filter gives better noise-free resolution.
The sinc4 filter also leads to better 50 Hz and 60 Hz rejection.
While the notch positions are not affected by the order of the
filter, the higher order filter has wider notches, which leads to
better rejection in the band (±1 Hz) around the notches. It also
gives better stop-band attenuation. The benefit of the sinc3 filter
is its lower settling time for the same output data rate.
Chop Disabled
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
fADC = fCLK/(1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK = master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to 4800 Hz;
that is, FS[9:0] can have a value from 1 to 1023.
The previous equation is valid for both the sinc3 and sinc4
filters. The settling time for the sinc4 filter is equal to
tSETTLE = 4/fADC
and the settling time for the sinc3 filter is equal to
tSETTLE = 3/fADC
Figure 19 and Figure 20 show the frequency response of the sinc4
filter and sinc3 filter, respectively, for an output data rate of 50 Hz.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
255075
100
125
150
FI
LT
E
R
G
A
IN
(
dB
)
FREQUENCY (Hz)
07
82
2-
0
13
Figure 19. Sinc4 Filter Response (50 Hz Output Data Rate)
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