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參數(shù)資料
| 型號(hào)： | AD7192BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CH SD 24-TSSOP |
| 設(shè)計(jì)資源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極；2 個(gè)差分，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極 |
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AD7192
Rev. A | Page 26 of 40
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F
IL
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d
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FREQUENCY (Hz)
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14
Figure 20. Sinc3 Filter Response (50 Hz Output Data Rate)
The sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of
120 dB, assuming a stable master clock, and the sinc3 filter gives
a rejection of 100 dB. The stop-band attenuation is, typically,
53 dB for the sinc4 filter but equal to 40 dB for the sinc3 filter.
The 3 dB frequency for the sinc4 filter is equal to
f3dB = 0.23 × fADC
and for the sinc3 filter, the 3 dB frequency is equal to
f3dB = 0.272 × fADC
Chop Enabled
With chop enabled, the ADC offset and offset drift are
minimized. When chop is enabled, the analog input pins are
continuously swapped. Therefore, with the analog input pins
connected in one direction, the settling time of the sinc filter is
allowed to elapse until a valid conversion is available. The analog
input pins are then inverted, and another valid conversion is
obtained. Subsequent conversions are then averaged so that the
offset is minimized. This continuous swapping of the analog
input pins and the averaging of subsequent conversions means
that the offset drift is also minimized.
Chopping affects the output data rate and settling time of the
ADC. For sinc4, the output data rate is equal to
fADC = fCLK/(4 × 1024 × FS[9:0])
For sinc3, the output data rate is equal to
fADC = fCLK/(3 × 1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK = master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The value of FS[9:0] can be varied from 1 to 1023. This results
in an output data rate of 1.173 Hz to 1200 Hz for the sinc4 filter
and 1.56 Hz to 1600 Hz for the sinc3 filter. The settling time for
sinc3 or sinc4 is equal to
tSETTLE = 2/fADC
Therefore, with chop enabled, the settling time is reduced for a
given output data rate compared to the chop disabled mode.
However, for a given FS[9:0] value, the output data rate is less
with chop enabled when compared with the chop disabled
mode. For either the sinc3 or sinc4 filter, the cutoff frequency f3dB is
equal to
f3dB = 0.24 × fADC
filter and sinc3 filter, respectively, when chop is enabled. As
shown in the plots, the stop-band attenuation is less when
compared with the chop disabled modes.
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LT
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R
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A
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FREQUENCY (Hz)
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Figure 21. Sinc4 Filter Response (Output Data Rate =12.5 Hz, Chop Enabled)
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FREQUENCY (Hz)
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Figure 22. Sinc3 Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled)
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