參數(shù)資料
型號： AD7192BRUZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 24/41頁
文件大?。?/td> 0K
描述： IC ADC 24BIT 2CH SD 24-TSSOP
設(shè)計資源： Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119)
標準包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 4.8k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個差分，單極；2 個差分，雙極；4 個偽差分，單極；4 個偽差分，雙極
AD7192
Rev. A | Page 29 of 40
Single Conversion Mode
line returns high after the first read operation. However, care
must be taken to ensure that the read operations are completed
before the next output update occurs. In continuous read mode,
the data register can be read only once.
In single conversion mode, the AD7192 is placed in power-
down mode after conversions. When a single conversion is
initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively,
in the mode register, the AD7192 powers up, performs a single
conversion, and then returns to power-down mode. The on-
chip oscillator requires 1 ms, approximately, to power up.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7192. The end of the conversion can be
monitored using the RDY bit or pin. This scheme is suitable for
interfacing to microcontrollers. If CS is required as a decoding
signal, it can be generated from a port pin. For microcontroller
interfaces, it is recommended that SCLK idle high between data
transfers.
DOUT/RDY goes low to indicate the completion of a conver-
sion. When the data-word has been read from the data register,
DOUT/RDY goes high. If CS is low, DOUT/RDY remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
DOUT/RDY has gone high.
The AD7192 can be operated with CS used as a frame synchro-
nization signal. This scheme is useful for DSP interfaces. In this
case, the first bit (MSB) is effectively clocked out by CS because
CS normally occurs after the falling edge of SCLK in DSPs. The
SCLK can continue to run between data transfers, provided the
timing numbers are obeyed.
If several channels are enabled, the ADC sequences through the
enabled channels and performs a conversion on each channel.
When a conversion is started, DOUT/RDY goes high and
remains high until a valid conversion is available. As soon as the
conversion is available, DOUT/RDY goes low. The ADC then
selects the next channel and begins a conversion. The user can
read the present conversion while the next conversion is being
performed. As soon as the next conversion is complete, the data
register is updated; therefore, the user has a limited period in
which to read the conversion. When the ADC has performed a
single conversion on each of the selected channels, it returns to
power-down mode.
The serial interface can be reset by writing a series of 1s to the
DIN input. If a Logic 1 is written to the AD7192 DIN line for at
least 40 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface gets lost due to a software error or some glitch in the
system. Reset returns the interface to the state in which it expects
a write to the communications register. This operation resets the
contents of all registers to their power-on values. Following a
reset, the user should allow a period of 500 μs before addressing
the serial interface.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
The AD7192 can be configured to continuously convert or to
perform a single conversion (see Figure 29 through Figure 31).
DIN
SCLK
DOUT/RDY
CS
0x08
0x58
DATA
0x280060
0
78
22-
021
Figure 29. Single Conversion
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