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參數(shù)資料
| 型號： | AD7192BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CH SD 24-TSSOP |
| 設(shè)計資源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極；4 個偽差分，單極；4 個偽差分，雙極 |
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AD7192
Rev. A | Page 28 of 40
is 50 Hz (sinc4 filter); 50 Hz rejection is no longer achieved. The
ADC must operate with an output data rate of 12.5 Hz to obtain
50 Hz rejection when zero latency is enabled. To obtain
simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode
register can be set when the output data rate is equal to 12.5 Hz.
The stop-band attenuation is considerably reduced also (3 dB
compared with 53 dB in the nonzero latency mode).
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0100
50
200
300
400
500
150
250
350
450
550 600
F
IL
T
E
R
GA
IN
(
d
B
)
FREQUENCY (Hz)
07
82
2-
0
20
Figure 27. Sinc4 Filter Response (50 Hz Output Data Rate, Zero Latency)
Channel Sequencer
The AD7192 includes a channel sequencer, which simplifies
communications with the device in multichannel applications.
The sequencer also optimizes the channel throughput of the
device because the sequencer switches channels at the optimum
rate rather than waiting for instructions via the SPI interface.
Bit CH0 to Bit CH7 in the configuration register are used to
enable the required channels. In continuous conversion mode,
the ADC selects each of the enabled channels in sequence and
performs a conversion on the channel. The RDY pin goes low
when a valid conversion is available on each channel. When
several channels are enabled, the contents of the status register
should be attached to the 24-bit word so that the user can
identify the channel that corresponds to each conversion. To
attach the status register value to the conversion, Bit DAT_STA
in the mode register should be set to 1.
When several channels are enabled, the ADC must allow the
complete settling time to generate a valid conversion each time
that the channel is changed. The AD7192 takes care of this:
when a channel is selected, the modulator and filter are reset
and the RDY pin is taken high. The AD7192 then allows the
complete settling time to generate the first conversion. RDY
goes low only when a valid conversion is available. The AD7192
then selects the next enabled channel and converts on that
channel. The user can then read the data register while the
ADC is performing the conversion on the next channel.
The time required to read a valid conversion from all enabled
channels is equal to
tSETTLE × number of enabled channels
For example, if the sinc4 filter is selected, chop is disabled, and
zero latency is disabled, the settling time for each channel is
equal to
tSETTLE = 4/fADC
where fADC is the output data rate when continuously converting
on a single channel. The time required to sample N channels is
4/(fADC × N)
RDY
CONVERSIONS
CHANNEL A
CHANNEL B
1/fADC
CHANNEL C
07822-
019
Figure 28. Channel Sequencer
DIGITAL INTERFACE
As indicated in the On-Chip Registers section, the program-
mable functions of the AD7192 are controlled using a set of
on-chip registers. Data is written to these registers via the serial
interface of the part. Read access to the on-chip registers is also
provided by this interface. All communication with the part must
start with a write to the communications register. After power-on
or reset, the device expects a write to its communications register.
The data written to this register determines whether the next oper-
ation is a read operation or a write operation and also determines
to which register this read or write operation occurs. Therefore,
write access to any of the other registers on the part begins with a
write operation to the communications register, followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register, followed by a read
operation from the selected register.
The serial interface of the AD7192 consists of four signals: CS,
DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer
data into the on-chip registers, and DOUT/RDY is used for
accessing data from the on-chip registers. SCLK is the serial clock
input for the device, and all data transfers (either on DIN or
DOUT/RDY) occur with respect to the SCLK signal.
The DOUT/RDY pin functions as a data ready signal also, the
line going low when a new data-word is available in the output
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of the
data register to indicate when not to read from the device, to
ensure that a data read is not attempted while the register is being
updated. CS is used to select a device. It can be used to decode the
AD7192 in systems where several components are connected to
the serial bus.
AD7192, with CS being used to decode the part.
shows
the timing for a read operation from the output shift register of
the AD7192, and
shows the timing for a write operation
to the input shift register. It is possible to read the same word
from the data register several times even though the DOUT/
RDY
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