參數(shù)資料
型號(hào)： AD7112
廠商： Analog Devices, Inc.
英文描述： ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75%
中文描述： LC2MOS LOGDAC雙對(duì)數(shù)D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 5/12頁(yè)
文件大?。?/td> 230K
代理商： AD7112
AD7112
REV. 0
–5–
CIRCUIT DE SCRIPT ION
GE NE RAL CIRCUIT INFORMAT ION
T he AD7112 consists of a dual 17-bit R-2R CMOS multiplying
D/A converter with extensive digital logic. Figure 1 shows a sim-
plified circuit of the D/A converter section of the AD7112. T he
logic translates the 8-bit binary input into a 17-bit word which is
used to drive the D/A converter. Figure 2 shows a typical circuit
configuration for the AD7112.
T he transfer function for the circuit of Figure 2 is given by:
V
O
=
±
V
IN
×
10exp ±0.375
N
20
or
V
O
V
IN
dB
=
±0.375
N
where 0.375 is the step size (resolution ) in dB and
N
is the
input code in decimal for values 0 to 239. For 240
≤
N
≤
255
the output is zero. T able I gives the output attenuation relative
to 0 dB for all possible input codes.
R
2R
V
IN
A
R
R
2R
2R
2R
2R
R
R
FB
A
OUT A
AGND
S1
S2
S3
S17
Figure 1. Simplified D/A Circuit of 1/2 AD7112
Figures 16 and 17 give a pictorial representation of the specified
accuracy and monotonic ranges for all grades of the AD7112.
High attenuation levels are specified with less accuracy than low
attenuation levels. T he range of monotonic behavior depends
upon the attenuation step size used. T o achieve monotonic op-
eration over the entire 88.5 dB range, it is necessary to select in-
put codes so that the attenuation step size at any point is
consistent with the step size guaranteed for monotonic opera-
tion at that point.
OUT A
AGND
DAC A
AD7112
DGND
CS
WR
R
FB
A
V
IN
A
DAC A/DAC B
V
DD
15
4
3
17
5
2
1
V
OUT
A1
C1
SIGNAL
GROUND
A1: 1/2 AD712
1/2 OP-275
6
16
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DATA INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE REQUIRED WHEN
USING HIGH SPEED AMPLIFIER.
Figure 2. Typical Circuit Configuration
T able I. Ideal Attenuation in dB vs. Input Code
D7–D4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0.000
6.000
12.000
18.000
0.375
6.375
12.375
18.375
0.750
6.750
12.750
18.750
1.125
7.125
13.125
19.125
1.500
7.500
13.500
19.500
1.875
7.875
13.875
19.875
2.250
8.250
14.250
20.250
2.625
8.625
14.625
20.625
3.000
9.000
15.000
21.000
3.375
9.375
15.375
21.375
3.750
9.750
15.750
21.750
4.125
10.125
16.125
22.125
4.500
10.500
16.500
22.500
4.875
10.875
16.875
22.875
5.250
11.250
17.250
23.250
5.625
11.625
17.625
23.625
0100
0101
0110
0111
24.000
30.000
36.000
42.000
24.375
30.375
36.375
42.375
24.750
30.750
36.750
42.750
25.125
31.125
37.125
43.125
25.500
31.500
37.500
43.500
25.875
31.875
37.875
43.875
26.250
32.250
38.250
44.250
26.625
32.625
38.625
44.625
27.000
33.000
39.000
45.000
27.375
33.375
39.375
45.375
27.750
33.750
39.750
45.750
28.125
34.125
40.125
46.125
28.500
34.500
40.500
46.500
28.875
34.875
40.875
46.875
29.250
35.250
41.250
47.250
29.625
35.625
41.625
47.625
1000
1001
1010
1011
48.000
54.000
60.000
66.000
48.375
54.375
60.375
66.375
48.750
54.750
60.750
66.750
49.125
55.125
61.125
67.125
49.500
55.500
61.500
67.500
49.875
55.875
61.875
67.875
50.250
56.250
62.250
68.250
50.625
56.625
62.625
68.625
51.000
57.000
63.000
69.000
51.375
57.375
63.375
69.375
51.750
57.750
63.750
69.750
52.125
58.125
64.125
70.125
52.500
58.500
64.500
70.500
52.875
58.875
64.875
70.875
53.250
59.250
65.250
71.250
53.625
59.625
65.625
71.625
1100
1101
1110
1111
72.000
78.000
84.000
MUT E
72.375
78.375
84.375
MUT E
72.750
78.750
84.750
MUT E
73.125
79.125
85.125
MUT E
73.500
79.500
85.500
MUT E
73.875
79.875
85.875
MUT E
74.250
80.250
86.250
MUT E
74.625
80.625
86.625
MUT E
75.000
81.000
87.000
MUT E
75.375
81.375
87.375
MUT E
75.750
81.750
87.750
MUT E
76.125
82.125
88.125
MUT E
76.500
82.500
88.500
MUT E
76.875
82.875
88.875
MUT E
77.250
83.250
89.250
MUT E
77.625
83.625
89.625
MUT E
D3D0
相關(guān)PDF資料
PDF描述
AD7112BN ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
AD7112BR LC2MOS LOGDAC Dual Logarithmic D/A Converter
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AD7112* LC2MOS LOGDAC Dual Logarithmic D/A Converter
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AD7112BR 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 17-bit 20-Pin SOIC W
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