參數(shù)資料
型號(hào): AD7112
廠商: Analog Devices, Inc.
英文描述: ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75%
中文描述: LC2MOS LOGDAC雙對(duì)數(shù)D / A轉(zhuǎn)換
文件頁(yè)數(shù): 4/12頁(yè)
文件大小: 230K
代理商: AD7112
AD7112
REV. 0
–4–
ABSOLUT E MAX IMUM RAT INGS*
V
DD
to AGND or DGND . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
OUT A, OUT B to AGND . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
IN
A, V
IN
B to AGND . . . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
V
RFB
A, V
RFB
B to AGND . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
Operating T emperature Range
All Versions . . . . . . . . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +150
°
C
Storage T emperature . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Power Dissipation, DIP . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
θ
JA
, T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 102
°
C/W
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300
°
C
Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
θ
JA
, T hermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75
°
C/W
Lead T emperature (Soldering)
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one Absolute Maximum Rating may be applied at any one time.
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7112 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
T E RMINOLOGY
RESOLUT ION: Nominal change in attenuation when moving
between two adjacent codes.
MONOT ONICIT Y: T he device is monotonic if the analog out-
put decreases or remains constant as the wdigital code in-
creases.
FEEDT HROUGH ERROR: T hat portion of the input signal
which reaches the output when all digital inputs are high.
OUT PUT CAPACIT ANCE: Capacitance from OUT A or
OUT B to ground.
GAIN ERROR: Gain error results from a mismatch between
R
FB
(the feedback resistance) and the R-2R ladder resistance.
Its effect in a LOGDAC is to produce a constant additive at-
tenuation error in dB over the whole range of the DAC.
ACCURACY: T he difference (measured in dB) between the
ideal transfer function as listed in T able I and the actual trans-
fer function as measured with the device.
DIGIT AL-T O-ANALOG GLIT CH IMPULSE: T he amount
of charge injected from the digital inputs to the analog output
when the inputs change state. T his is normally specified as the
area of the glitch in either pA-s or nV-s depending on whether
the glitch is measured as a current or voltage signal. Glitch im-
pulse is measured with V
IN
= AGND.
ORDE RING INFORMAT ION
Specified
Accuracy
Range
T emperature
Range
Package
Option*
Model
AD7112BN
AD7112CN
AD7112BR
AD7112CR
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
0 dB to 60 dB
0 dB to 72 dB
0 dB to 60 dB
0 dB to 72 dB
N-20
N-20
R-20
R-20
*N = Plastic DIP; R = SOIC.
PIN FUNCT ION DE SCRIPT ION
Pin
Mnemonic
Description
1
2
3
4
5
6
AGND
OUT A
R
FB
A
V
IN
A
DGND
DAC A
/
DAC B
Analog Ground.
Current Output T erminal of DAC A.
Feedback Resistor for DAC A.
Reference Input to DAC A
Digital Ground.
Selects Which DAC Can Accept Data from
Input Port.
8 Data Inputs.
Chip Select Input, Active Low.
Write Input, Active Low.
Power Supply Input 5 V
±
5%.
Reference Input to DAC B.
Feedback Resistor for DAC B.
Current Output T erminal of DAC B.
7–14 DB7–DB0
15
CS
16
WR
17
V
DD
18
V
IN
B
19
R
FB
B
20
OUT B
PIN CONFIGURAT ION
DIP/SOIC
AGND
OUT A
DGND
(MSB) DB7
DAC A/DAC B
DB6
DB5
DB4
R
FB
A
V
IN
A
OUT B
R
FB
B
V
IN
B
V
DD
DB0 (LSB)
DB1
DB2
DB3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
(Not to Scale)
AD7112
WR
CS
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