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參數(shù)資料
| 型號(hào)： | AD7112 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | LC2MOS LOGDAC雙對(duì)數(shù)D / A轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 230K |
| 代理商： | AD7112 |
AD7112
REV. 0
–10–
MICROPROCE SSOR INT E RFACING
Figures 18 to 20 show interfaces between the AD7112 and
three popular 8-bit microprocessor systems, the MC68008,
8085A/8088 and the 8051. In the MC68008 and 8085/8088 in-
terfaces, the AD7112 is memory mapped with separate ad-
dresses for each DAC.
AD7112-8085A/8088 INT E RFACE
Figure 18 shows a connection diagram for interfacing the
AD7112 to both the 8085A and the 8088 microprocessors. T his
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. T he
AD7112 is memory mapped with separate memory addresses
for DAC A and DAC B.
8085A / 8088
AD7112*
CS
WR
DB7 – DB0
DATA BUS
A15 – A8
AD7 – AD0
ALE
ADDRESS BUS
WR
DEN
DAC A / DAC B
A**
A+1**
ADDRESS
DECODE
LOGIC
8-BIT
LATCH
*
ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY.
** A = DECODED ADDRESS FOR AD7112 DAC A
A+1 = DECODED ADDRESS FOR AD7112 DAC B
Figure 18. AD7112–8085A/8088 Interface Circuit
AD7112–68008 INT E RFACE
Figure 19 shows a connection diagram for interfacing the
AD7112 to the 68008 microprocessor. T he AD7112 is again
memory mapped with separate memory addresses for DAC A
and DAC B.
AD7112*
CS
WR
DB7 – DB0
DATA BUS
ADDRESS BUS
DAC A / DAC B
A**
A+1**
ADDRESS
DECODE
LOGIC
*
ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY.
** A = DECODED ADDRESS FOR AD7112 DAC A
A+1 = DECODED ADDRESS FOR AD7112 DAC B
68008
A23 – A1
D7 – D0
R /W
AS
DTACK
Figure 19. AD7112–68008 Interface Circuit
AD7112–8051 INT E RFACE
Figure 20 shows a connection diagram between the AD7112
and the 8051 microprocessor. T he AD7112 is port mapped in
this interface. T he loading structure is as follows: Data to be
loaded to the DAC is output to Port 1: P3.0, P3.1 and P3.2 are
bit addressable port lines and are used to control the DAC
select,
CS
and
WR
inputs. A sample routine for writing to DAC A
is shown below.
MOV A,DAT A;
CLR 3.2;
CLR 3.0;
CLR 3.1;
MOV A,P1;
SET B 3.1;
SET B 3.0;
Data to be written is loaded to the accumulator.
Select DAC A.
Bring
CS
low.
Bring
WR
low.
Write data to DAC.
Deactivate
WR
.
Deactivate
CS
8051
P3.0
P3.1
P3.2
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AD7112*
CS
WR
DAC A / DAC B
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
* ANALOG CIRCUITRY OMITTED FOR CLARITY
Figure 20. AD7112–8051 Interface Circuit
APPLIC AT IONS
Automatic Gain Control
In an automatic gain control system an input signal is attenuated
or amplified so that its average output level remains constant.
T he AD7112 D/A converter is used here as a variable gain or at-
tenuation element that adjusts the output signal relative to the
input level.
A feedback loop consisting of a detector, comparator, and up/
down counter continuously adjusts the contents of the counter
and hence the gain or attenuation of the circuit so that the signal
level at the output remains constant and equal to the reference
input signal. T he negative feedback action of the loop ensures
that the average output voltage of the automatic gain control
system remains constant. Figure 21 shows a block diagram of a
typical AGC control loop using 1/2 AD7112 as the gain/ attenu-
ation element.
Whenever the input signal is outside the dynamic range of the
programmable gain element in the AGC loop, there should be a
stable, well defined input output relationship.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7112BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7112BR | LC2MOS LOGDAC Dual Logarithmic D/A Converter |
| AD7112CN | LC2MOS LOGDAC Dual Logarithmic D/A Converter |
| AD7112CR | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7112* | LC2MOS LOGDAC Dual Logarithmic D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD71124JCFZ | 制造商:Analog Devices 功能描述:IC |
| AD7112BN | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 17-bit 20-Pin PDIP N Tube 制造商:Analog Devices 功能描述:IC 17BIT DAC DUAL LOG 7112 DIP20 |
| AD7112BNZ | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 17-bit 20-Pin PDIP N Tube |
| AD7112BR | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 17-bit 20-Pin SOIC W |
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