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| 型號： | AD7112 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | LC2MOS LOGDAC雙對數(shù)D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 230K |
| 代理商： | AD7112 |
REV. 0
–2–
AD7112–SPECIFICATIONS
(V
DD
= +5 V
6
5%; OUT A = OUT B = AGND = DGND = 0 V; V
IN
A = V
IN
B = 10 V.
Output amplifier AD712 except where noted. All specifications T
MN
to T
MAX
unless otherwse noted.)
C Version
1
T
A
=
T
A
=
T
A
=
Parameter
+25
8
C
T
MIN
, T
MAX
+25
8
C
B Version
T
A
=
T
MIN
, T
MAX
Units
Conditions/Comments
ACCURACY
Resolution
Accuracy Relative to
0 dB Attenuation
0.375 dB Steps:
Accuracy
≤
±
0.17 dB
Monotonic
0.75 dB Steps:
Accuracy
≤
±
0.35 dB
Monotonic
1.5 dB Steps:
Accuracy
≤
±
0.7 dB
Monotonic
3.0 dB Steps:
Accuracy
≤
±
1.4 dB
Monotonic
6.0 dB Steps:
Accuracy
≤
±
2.7 dB
Monotonic
Gain Error
0.375
0.375
0.375
0.375
dB
Guaranteed Attenuation
Ranges for Specified Step Sizes.
0 to 36
0 to 54
0 to 36
0 to 54
0 to 30
0 to 48
0 to 30
0 to 48
dB min
dB min
0 to 48
0 to 72
0 to 42
0 to 66
0 to 42
0 to 72
0 to 36
0 to 60
dB min
dB min
0 to 54
Full Range 0 to 78
0 to 48
0 to 48
0 to 85.5
0 to 42
0 to 72
dB min
dB min
Full Range Is 0 dB to 88.5 dB.
0 to 66
Full Range Full Range
0 to 54
0 to 60
Full Range Full Range
0 to 48
dB min
dB min
0 to 72
Full Range Full Range
±
0.1
0 to 60
0 to 60
Full Range Full Range
±
0.15
0 to 60
dB min
dB min
dB max
±
0.15
±
0.2
Measured Using R
FB
A,
R
FB
B. Both DAC Registers
Loaded With All 0s.
Output Leakage Current
OUT A, OUT B
Input Resistance,
V
IN
A, V
IN
B
Input Resistance Match
Feedback Resistance,
R
FB
A, R
FB
B
±
50
±
400
±
50
±
400
nA max
9/15
±
1
9/15
±
1
9/15
±
2
9/15
±
2
k
min/max T ypically 12 k
.
% max
9.3/15.7
9.3/15.7
9.3/15.7
9.3/15.7
k
min/max
LOGIC INPUT S
CS
,
WR
,
DAC A
/DAC B,
DB0–DB7
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Leakage Current
Input Capacitance
2
0.8
2.4
±
1
10
0.8
2.4
±
10
10
0.8
2.4
±
1
10
0.8
2.4
±
10
10
V max
V min
μ
A max
pF max
POWER REQUIREMENT S
V
DD
, Range
3
4.75/5.25
2
2
4.75/5.25
2
2
4.75/5.25
2
2
4.75/5.25
2
2
V min/max
mA max
mA max
For Specified Performance.
Logic Inputs = V
IL
or V
IH
Logic Inputs = 0 V or V
DD
NOT ES
l
T emperature range as follows: B, C Versions: –40
°
C to +85
°
C.
2
Guaranteed by design, not production tested.
3
T he part will function with V
DD
= 5 V
±
10% with degraded performance.
Specifications subject to change without notice.
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| AD7112BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
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| AD7112CR | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
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| AD7112BR | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 17-bit 20-Pin SOIC W |
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