- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373890 > AD6624A (Analog Devices, Inc.) Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) PDF資料下載
參數(shù)資料
| 型號： | AD6624A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | 四通道，100 MSPS的數(shù)字接收信號處理器（RSP） |
| 文件頁數(shù)： | 35/40頁 |
| 文件大小： | 636K |
| 代理商： | AD6624A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當前第35頁第36頁第37頁第38頁第39頁第40頁
REV. 0
AD6624A
–35–
Bits 3
–
0
control the state of each of the channels. Each bit corre-
sponds to one of the possible RSP channels within the device. If
this bit is cleared, the channel operates normally. However,
when this bit is set, the indicated channel enters a low power
sleep mode.
Bit 4
causes the normal RSP data on serial channel 0 to be
replaced with read access data. This allows reading the internal
registers over the serial bus. It should be noted that in the mode,
any RSP data will be superceded by internal access data.
Bit 5
allows access to the Input Control Port Registers at channel
addresses 00-07. When this bit is set low, the normal memory
map is accessed. However, when this bit is set, it allows access
to the Input Port Control Registers. Access to these registers
allows the lower and upper thresholds to be set along with dwell
time and other features. When this bit is set, the value in external
address 6 (CAR) points to the memory map for the Input Port
Control Registers instead of the normal memory map. See Input
Port Control Registers below.
Bits 6
–
7
are reserved and should be set low.
Data Address Registers
External Address [2-0] form the data registers DR2, DR1, and
DR0 respectively. All internal data words have widths that are
less than or equal to 20 bits. Accesses to External Address [0]
DR0 trigger an internal access to the AD6624A based on the
address indicated in the ACR and CAR. Thus during writes to
the internal registers, External Address [0] DR0 must be written
last. At this point, data is transferred to the internal memory
indicated in A[9:0]. Reads are performed in the opposite direction.
Once the address is set, External Address [0] DR0 must be the
first data register read to initiate an internal access. DR2 is only
four bits wide. Data written to the upper four bits of this register
will be ignored. Likewise, reading from this register will produce
only four LSBs.
Write Sequencing
Writing to an internal location is achieved by first writing the
upper two bits of the address to Bits 1 through 0 of the ACR.
Bits 7:2 may be set to select the channel as indicated above. The
CAR is then written with the lower eight bits of the internal
address (it does not matter if the CAR is written before the
ACR as long as both are written before the internal access).
Data Register 2, (DR2) and Data Register 1 (DR1) must be
written first because the write to Data Register DR0 triggers the
internal access. Data Register DR0 must always be the last
register written to initiate the internal write.
Read Sequencing
Reading from the microport is accomplished in the same manner.
The internal address is set up the same way as the write. A read
from Data Register DR0 activates the internal read, thus register
DR0 must always be read first to initiate an internal read followed
by DR1 and DR2. This provides the eight LSBs of the internal
read through the microport (D[7:0]). Additional data registers
can be read to read the balance of the internal memory.
Read/Write Chaining
The microport of the AD6624A allows for multiple accesses
while
CS
is held low (
CS
can be tied permanently low if the
microport is not shared with additional devices). The user can
access multiple locations by pulsing the
WR
or
RD
line and
changing the contents of the external 3-bit address bus. External
access to the external registers of Table II is accomplished in
one of two modes using the
CS
,
RD
,
WR
, and MODE inputs.
The access modes are Intel Nonmultiplexed Mode and Motorola
Nonmultiplexed Mode. These modes are controlled by the
MODE input (MODE = 0 for INM, MODE = 1 for MNM).
CS
,
RD
, and
WR
control the access type for each mode.
Intel Nonmultiplexed Mode (INM)
MODE must be tied low to operate the AD6624A microprocessor
in INM mode. The access type is controlled by the user with
the
CS
,
RD
(
DS
), and
WR
(RW) inputs. The RDY (
DTACK
)
signal is produced by the microport to communicate to the user
that an access has been completed. RDY (
DTACK
) goes low at
the start of the access and is released when the internal cycle is
complete. See the timing diagrams for both the read and write
modes in the specifications.
Motorola Nonmultiplexed Mode (MNM)
MODE must be tied high to operate the AD6624A microprocessor
in MNM mode. The access type is controlled by the user with
the
CS,
DS
(
RD
), and RW(
WR
) inputs. The
DTACK
(RDY)
signal is produced by the microport to communicate to the user
that an access has been completed.
DTACK
(RDY) goes low
when an internal access is complete and then will return high
after
DS
(
RD
) is deasserted. See the timing diagrams for both
the read and write modes in the specifications.
Table XIII. Memory Map for Input Port Control Registers
Ch Address
Register
Bit Width
Comments
00
01
02
03
Lower Threshold A
Upper Threshold A
Dwell Time A
Gain Range A Control Register
10
10
20
5
9
–
0:
9
–
0:
19
–
0:
4:
3:
2
–
0:
9
–
0:
9
–
0:
19
–
0:
4:
3:
2
–
0:
Lower Threshold for Input A
Upper Threshold for Input A
Minimum Time below Lower Threshold A
Output Polarity LIA-A and LIA-B
Interleaved Channels
Linearization Hold-Off Register
Lower Threshold for Input B
Upper Threshold for Input B
Minimum Time below Lower Threshold B
Output Polarity LIB-A and LIB-B
Interleaved Channels
Linearization Hold-Off Register
04
05
06
07
Lower Threshold B
Upper Threshold B
Dwell Time B
Gain Range B Control Register
10
10
20
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6624AABC | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6630AR-REEL | Differential, Low Noise IF Gain Block with Output Clamping |
| AD6630AR | Differential, Low Noise IF Gain Block with Output Clamping |
| AD6630PCB | Differential, Low Noise IF Gain Block with Output Clamping |
| AD6630R | Differential, Low Noise IF Gain Block with Output Clamping |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6624AABC | 制造商:Advanced Micro Devices 功能描述: |
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD6624AS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
發(fā)布緊急采購，3分鐘左右您將得到回復。