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參數(shù)資料
| 型號： | AD6624A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | 四通道，100 MSPS的數(shù)字接收信號處理器（RSP） |
| 文件頁數(shù)： | 11/40頁 |
| 文件大小： | 636K |
| 代理商： | AD6624A |
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REV. 0
AD6624A
–11–
PIN FUNCTION DESCRIPTIONS 196-LEAD BGA
Pin No.
Type
Function
POWER SUPPLY
VDD
VDDIO
GND
P
P
G
2.5 V Supply
3.3 V IO Supply
Ground
INPUTS
INA[13:0]
1
EXPA[2:0]
1
IENA
2
INB[13:0]
1
EXPB[2:0]
1
IENB
2
RESET
CLK
SYNCA
1
SYNCB
1
SYNCC
1
SYNCD
1
SDIN0
1
SDIN1
1
SDIN2
1
SDIN3
1
CS
1
CHIP_ID[3:0]
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
A Input Data (Mantissa)
A Input Data (Exponent)
Input Enable—Input A
B Input Data (Mantissa)
B Input Data (Exponent)
Input Enable—Input B
Active Low Reset Pin
Input Clock
All Sync Pins Go to All Four Output Channels
All Sync Pins Go to All Four Output Channels
All Sync Pins Go to All Four Output Channels
All Sync Pins Go to All Four Output Channels
Serial Data Input—Channel 0
Serial Data Input—Channel 1
Serial Data Input—Channel 2
Serial Data Input—Channel 3
Chip Select
Chip ID Selector
CONTROL
SBM0
1
SCLK0
1
SCLK1
1
SCLK2
1
SCLK3
1
SDIV[3:0]
1
SDFS0
1
SDFS1
1
SDFS2
1
SDFS3
1
SDFE0
SDFE1
SDFE2
SDFE3
I
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
O
O
O
O
Serial Bus Master—Channel 0 only
Bidirectional Serial Clock—Channel 0
Bidirectional Serial Clock—Channel 1
Bidirectional Serial Clock—Channel 2
Bidirectional Serial Clock—Channel 3
Serial Clock Divisor—Channel 0
Bidirectional Serial Data Frame Sync—Channel 0
Bidirectional Serial Data Frame Sync—Channel 1
Bidirectional Serial Data Frame Sync—Channel 2
Bidirectional Serial Data Frame SyncvChannel 3
Serial Data Frame End—Channel 0
Serial Data Frame End—Channel 1
Serial Data Frame End—Channel 2
Serial Data Frame End—Channel 3
MICROPORT CONTROL
D[7:0]
A[2:0]
DS
(
RD
)
DTACK
(RDY)
2
RW (
WR
)
MODE
I/O/T
I
I
O/T
I
I
Bidirectional Microport Data
Microport Address Bus
Active Low Data Strobe (Active Low Read)
Active Low Data Acknowledge (Microport Status Bit)
Read Write (Active Low Write)
Intel or Motorola Mode Select
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|---|---|
| AD6624AABC | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
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| AD6630AR | Differential, Low Noise IF Gain Block with Output Clamping |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD6624AABC | 制造商:Advanced Micro Devices 功能描述: |
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD6624AS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
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