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參數(shù)資料
| 型號： | AD5379ABCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CHAN 108CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 850mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 108-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 108-CSPBGA（13x13） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 40 電壓，雙極 |
| 采樣率（每秒）： | 50k |
| 配用： | EVAL-AD5379EBZ-ND - BOARD EVALUATION FOR AD5379 |
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AD5379
Rev. B | Page 13 of 28
Table 8. Pin Function Descriptions
Pin
Function
VCC(1–3)
Logic Power Supply; 2.7 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
VSS(1–5)
Negative Analog Power Supply; 11.4 V to 16.5 V for Specified Performance. These pins should be decoupled with
0.1 μF ceramic capacitors and 10 μF capacitors.
VDD(1–5)
Positive Analog Power Supply; +11.4 V to +16.5 V for Specified Performance. These pins should be decoupled with
0.1 μF ceramic capacitors and 10 μF capacitors.
AGND(1–4)
Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.
DGND(1–4)
Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.
VREF1(+), VREF1()
Reference Inputs for DACs 0 to 7, 10 to 17, 20 to 27, and 30 to 37. These voltages are referred to AGND.
VREF2(+), VREF2()
Reference Inputs for DACs 8, 9, 18, 19, 28, 29, 38, and 39. These reference voltages are referred to AGND.
VBIAS
DAC Bias Voltage Input/Output. This pin provides an access to the on-chip voltage generator voltage and is provided
for bypassing and overdriving purposes only. If VREF(+) > 4.25 V, VBIAS must be pulled high externally to an equal or
higher potential (for example, 5 V). If VREF(+) < 4.25 V, the on-chip bias generator can be used. In this case, the VBIAS pin
should be decoupled with a 10 nF capacitor to AGND.
VOUT0 to VOUT39
DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output is capable of driving an
output load of 5 kΩ to ground. Typical output impedance of these amplifiers is 1 Ω.
SER/PAR
Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. This pin has an
internal 1 MΩ pull-down resistor, meaning that the default state at power-on is parallel mode. If this pin is tied high,
the serial interface is used.
Active Low Input. This is the frame synchronization signal for the serial interface.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds
up to 50 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
SDO1
Serial Data Output. CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked
out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
Daisy-Chain Select Input (Level Sensitive, Active High). When high, this signal is used in conjunction with SER/PAR
high to enable serial interface daisy-chain mode.
CS
Parallel Interface Chip Select Input (Level Sensitive, Active Low). If this pin is low, the device is selected.
WR
Parallel Interface Write Input (Edge Sensitive). The rising edge of WR is used in conjunction with CS low and the
address bus inputs to write to the selected AD5379 registers.
DB13 to DB0
Parallel Data Inputs. The AD5379 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB
and DB0 is the LSB.
A0 to A7
Parallel Address Inputs. A7 to A4 are decoded to select one group or multiple groups of registers (input registers, gain
registers (m) or offset registers (c)) for a data transfer. This pin is used in conjunction with the REG1 and REG0 pins to
determine the destination register for the input data. See the Parallel Interface section for details of the address
decoding.
REG0
Parallel Interface Register Select Input. This pin is used together with REG1 to select data registers, gain registers,
offset registers, increment/decrement mode, or the soft reset function. See Table 11.
CLR
Asynchronous Clear Input (Level Sensitive, Active Low). When CLR is low, the input to each of the DAC output buffer
stages, VOUT0 to VOUT39, is switched to the externally set potential on the relevant REFGND pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the DAC outputs remain cleared until LDAC is taken low. The
contents of input registers and DAC registers 0 to 39 are not affected by taking CLR low.
BUSY
Digital Input/Open-Drain Output. This pin must be pulled high with a pull-up resistor for correct operation. BUSY goes
low during internal calculations of x2. During this time, the user can continue writing new data to additional ×1, c,
and m registers (these are stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take
place. If LDAC is taken low while BUSY is low, this event is stored. Because BUSY is bidirectional, it can be pulled low
externally to delay LDAC action. BUSY also goes low during power-on reset or when the RESET pin is low. During a
RESET operation, the parallel interface is disabled and any events on LDAC are ignored.
LDAC
Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input
registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is
active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when
BUSY goes inactive. However, any events on LDAC during power-on reset or RESET are ignored.
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