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參數(shù)資料
| 型號(hào)： | AD5379ABCZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/29頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 40CHAN 108CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 850mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 108-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 108-CSPBGA（13x13） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 40 電壓，雙極 |
| 采樣率（每秒）： | 50k |
| 配用： | EVAL-AD5379EBZ-ND - BOARD EVALUATION FOR AD5379 |
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AD5379
Rev. B | Page 22 of 28
INTERFACES
The AD5379 contains a serial and a parallel interface. The
active interface is selected via the SER/PAR pin.
The AD5379 uses an internal FIFO memory to allow high
speed successive writes in both serial and parallel modes. The
user can continue writing new data to the AD5379 while write
instructions are being executed. The BUSY signal goes low while
instructions in the FIFO are being executed. Up to 120 successive
instructions can be written to the FIFO at maximum speed.
When the FIFO is full, additional writes to the AD5379 are
ignored.
To minimize both the power consumption of the device and
on-chip digital noise, the active interface powers up fully only
when the device is being written to, that is, on the falling edge
of WR or on the falling edge of SYNC.
All digital interfaces are 2.5 V LVTTL-compatible when
operating from a 2.7 V to 3.6 V VCC supply.
PARALLEL INTERFACE
A pull-down on the SER/PAR pin makes the parallel interface
the default. If using the parallel interface, the SER/PAR pin can
be left unconnected.
shows the timing diagram for a
parallel write to the AD5379. The parallel interface is controlled
by the following pins.
CS Pin
Active low device select pin.
WR Pin
On the rising edge of WR, with CS low, the address values at
Pin A7 to Pin A0 are latched, and data values at Pin DB13 to
Pin DB0 are loaded into the selected AD5379 input registers.
REG1, REG0 Pins
The REG1 and REG0 pins determine the destination register of
the data being written to the AD5379. See Table 11.
Table 11. Register Selection
REG1
REG0
Register Selected
1
Input data register (x1)
1
0
Offset register (c)
0
1
Gain register (m)
0
Special function register
DB13 to DB0 Pins
The AD5379 accepts a straight, 14-bit parallel word on Pin DB0
to Pin DB13, where Pin DB13 is the MSB and Pin DB0 is the
A7 to A0 Pins
Each of the 40 DAC channels can be individually addressed. In
addition, several channel groupings enable the user to simulta-
neously write the same data to multiple DAC channels. Address
Bits A7 to A4 are decoded to select one group or multiple
groups of registers. Address Bits A3 to A0 select one of ten
input data registers (x1), offset registers (c), or gain registers
(m). See Table 17.
SERIAL INTERFACE
The SER/PAR pin must be tied high to enable the serial inter-
face and disable the parallel interface. The serial interface is
controlled by five pins, as follows.
SYNC, DIN, SCLK
Standard 3-wire interface pins.
DCEN
Selects standalone mode or daisy-chain mode.
SDO
Data out pin for daisy-chain mode.
write to the AD5379 in standalone and daisy-chain modes,
respectively.
The 24-bit data word format for the serial interface is shown in
MSB
REG0
DB13–DB0
LSB
A7–A0
REG1
REGISTER DATA BITS
GROUP/CHANNEL
SELECT BITS
REGISTER SELECT
BITS
03165-021
Figure 21. Serial Data Format
Standalone Mode
By connecting the DCEN (daisy-chain enable) pin low,
standalone mode is enabled. The serial interface works with
both a continuous and a burst serial clock. The first falling edge
of SYNC starts the write cycle and resets a counter that counts
the number of serial clocks to ensure that the correct number of
bits is shifted into the serial shift register. Additional edges on
SYNC are ignored until 24 bits are shifted into the register.
Once 24 bits are shifted into the serial shift register, the SCLK is
ignored. In order for another serial transfer to take place, the
counter must be reset by the falling edge of SYNC.
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