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參數(shù)資料
| 型號(hào)： | AD5379ABCZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CHAN 108CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 850mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 108-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 108-CSPBGA（13x13） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 40 電壓，雙極 |
| 采樣率（每秒）： | 50k |
| 配用： | EVAL-AD5379EBZ-ND - BOARD EVALUATION FOR AD5379 |
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AD5379
Rev. B | Page 21 of 28
FIFO VS. NON-FIFO OPERATION
Two modes of operation are available for loading data to the
AD5379 registers: operation with FIFO disabled and operation
with FIFO enabled. Operation with FIFO disabled is optimum
for single writes to the device. If the system requires significant
data transfers to the AD5379, however, then operation with
FIFO enabled is more efficient.
When FIFO is enabled, the AD5379 uses an internal FIFO
memory to allow high speed successive writes in both serial and
parallel modes. This optimizes the interface speed and efficiency,
minimizes the total conversion time due to internal digital
efficiencies, and minimizes the overhead on the master con-
troller when managing the data transfers. The BUSY signal goes
low while instructions in the state machine are being executed.
Table 10 compares operation with FIFO enabled and FIFO
disabled for different data transfers to the AD5379. Operation
with FIFO enabled is more efficient for all operations except
single write operations. When using the FIFO, the user can
continue writing new data to the AD5379 while write instruc-
tions are being executed. Up to 128 successive instructions can
be written to the FIFO at maximum speed. When the FIFO is
full, additional writes to the AD5379 are ignored.
BUSY INPUT FUNCTION
If required, because the BUSY pin is bidirectional and open-
drain , a second AD5379 (or other device, such as a system
controller), can pull
BUSY low to delay DAC update(s). This is a
means of delaying any LDAC action. This feature allows
synchronous updates of multiple AD5379 devices in a system, at
maximum speed. As soon as the last device connected to the
BUSY pin is ready, all DACs update automatically. Tying the
BUSY pin of multiple devices together enables synchronous
updating of all DACs without extra hardware.
POWER-ON RESET FUNCTION
The AD5379 contains a power-on reset generator and state
machine. During power-on, CLR becomes active (internally),
the power-on state machine resets all internal registers to their
default values, and BUSY goes low. This sequence takes 8 ms
(typical). The outputs, VOUT0 to VOUT39, are switched to the
externally set potential on the REFGND pin. During power-on,
the parallel interface is disabled, so it is not possible to write to
the part. Any transitions on LDAC during the power-on period
are ignored in order to reject initial LDAC pin glitching. A
rising edge on BUSY indicates that power-on is complete and
that the parallel interface is enabled. All DACs remain in their
power-on state until LDAC is used to update the DAC outputs.
RESET INPUT FUNCTION
The AD5379 can be placed in its power-on reset state at any
time by activating the RESET pin. The AD5379 state machine
initiates a reset sequence to digitally reset the x1, m, c, and x2
registers to their default power-on values. This sequence takes
95 μs (typical), 120 μs (maximum), 70 μs (minimum). During
this sequence, BUSY goes low. While RESET is low, any
transitions on LDAC are ignored. As with the CLR input, while
RESET is low, the DAC outputs are switched to REFGND. The
outputs remain at REFGND until an LDAC pulse is applied.
This reset function can also be implemented via the parallel
interface by setting the REG0 and REG1 pins low and writing
all 1s to DB13 to DB0 (see
for soft reset).
INCREMENT/DECREMENT FUNCTION
The AD5379 has a special function register that enables the user
to increment or decrement the internal 14-bit input register
data (x1) in steps of 0 to 127 LSBs. The increment/decrement
function is selected by setting both REG1 and REG0 pins (or
bits) low. Address Pins (or Bits) A7 to A0 are used to select a
DAC channel or group of channels. The amount by which the
x1 register is incremented or decremented is determined by the
DB6 to DB0 bits/pins. For example, for a 1 LSB increment or
decrement, DB6 to DB0 = 0000001, while for a 7 LSB increment
or decrement, DB6 to DB0 = 0000111. DB8 determines whether
the input register data is incremented (DB8 = 1) or decre-
mented (DB8 = 0). The maximum amount by which the user is
allowed to increment or decrement the data is 127 LSBs, that is,
DB6 to DB0 = 1111111. The 0 LSB step is included to facilitate
software loops in the user’s application. See Table 15.
The AD5379 has digital overflow and underflow detection
circuitry to clamp at full scale or zero scale when the values
chosen for increment or decrement mode are out of range.
1 For correct operation, use pull-up resistor to digital supply.
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