參數(shù)資料
型號(hào)： AD1849KP
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Serial-Port 16-Bit SoundPort Stereo Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 19/28頁(yè)
文件大小： 293K
代理商： AD1849KP
AD1849K
REV. 0
–19–
Daisy-Chaining Multiple Codecs
Up to four SoundPort Codecs can be daisy-chained with frame
sizes in multiples of 64 bits. T he serial data is time-division
multiplexed (T DM), allocating each Codec its own 64-bit word
in the frame.
T he pins that support T DM daisy-chaining of multiple Codecs
are the word chaining input (T SIN) and the word chaining out-
put (T SOUT ). As described above, T SIN is used to indicate
the position of the first bit of a particular Codec’s 64-bit word
within the total frame.
T he word chaining output (T SOUT ) is generated by every
Codec during the transmission of the last bit of its 64-bit word.
T he first device in any Codec chain uses an externally generated
or self-generated FSYNC signal as an input to T SIN. T he
T SOUT of the first Codec is wired directly to the T SIN of the
second Codec and so on. T he waveform of T SOUT is a pulse of
one SCLK period in duration. All Codecs share the same
SCLK , FSYNC, SDRX , and SDT X lines since they are select-
ing different words from a common frame.
Note that a powered-down Codec immediately echoes T SIN on
T SOUT . T hus, a Codec can be added or removed from the
chain simply by using the PDN pin. See “Reset and Power
Down” below for more details. See Figure 9 for an illustration
of daisy-chained Codecs.
EXTERNAL
DEVICE
SCLK
SDTX
SDRX
FSYNC
AD1849K #1
MASTER
SCLK
SDRX
SDTX
FSYNC
TSIN
TSOUT
D/C
PDN
RESET
AD1849K #2
SLAVE
SCLK
SDRX
SDTX
FSYNC
TSIN
TSOUT
D/C
CLKOUT
CLKIN
D/C
PDN1
PDN2
RESET
PDN
RESET
Figure 9. AD1849K Daisy-Chaining
Note that at most, one Codec in a daisy-chain can be in master
mode without contention. All other Codecs must be in slave
mode, receiving SCLK and T SIN externally.
Each slave can use SCLK as its clock source. However, as an
alternative, it is possible to connect the CLK OUT pin of the
master Codec to the CLK IN pins of the slaves, so that the sam-
ple frequency selected by the master (from one of its two crys-
tals) will be automatically applied to the slaves. T he master
must be programmed for the desired sample frequency and the
correct number of bits per frame. T he slaves must be pro-
grammed for CLK IN as the clock source, the correct number of
bits per frame, and SCLK as an input. T he slaves FSYNC out-
puts will be three-stated and thus can be connected to the
master’s FSYNC without contention.
If SCLK is the clock source, it must run at 256
×
F
S
, and
therefore the frame size must be 256 bits, i.e., four words. By
contrast, if the master Codec’s CLK OUT is used as the clock
source, then it can run at either 256
×
F
S
or 128
×
F
S
.
Parallel I/O Bits
Both Data and Control Words allocate Bit positions for
“parallel I/O,” PIO1:0. T his provides a convenient mechanism
for transferring signaling information between the serial data
and control streams and the external pair of bidirectional pins
also named “PIO1” and “PIO0.” T he states of the parallel I/O
bits and pins do not affect the internal operation of the Codec in
any way; their exclusive use is for system signaling.
T he PIO pins are open-drain and should be pulled HI exter-
nally. T hey can be read (through serial output data) in either
Control or Data Mode and can be written (through serial input
data) in Data Mode exclusively. T he values in the PIO field of
the Control Word serial input in Control Mode will be ignored.
An external device may drive either PIO pin LO even when
written HI by the Codec, since the pin outputs are open-drain.
T hus, a PIO value read back as a serial output bit may differ
from the value just written as a serial input bit.
T he PIO pins are read on the rising edge of SCLK five (5)
SCLK periods before the first PIO bit is transmitted out over
the serial interface. In Data Mode, the PIO pins are sampled as
Bit 20 starts to be driven out. In Control Mode, the PIO pins
are sampled as Bit 36 starts being driven out. T iming para-
meters are as shown in Figure 7; PIO pin input data is relative
to the rising edge of SCLK . (Note that
only
the PIO pins are
read on SCLK
rising
edges.)
T he PIO pins are driven very shortly after the PIO data bits in
the input Data Word are read (Data Mode only). T hey are
driven on the
falling
edge of SCLK (unlike any other output).
T he PIO data bits in the input are located at Bits 15 and 14 in
the Data Word and at Bits 31 and 30 in the Control Word
(Figure 8). Due to the five (5) SCLK period delay, the PIO pins
will be driven out with new values for Data Mode on the SCLK
falling edge when Bit 8 is read in, and for Control Mode on the
SCLK falling edge when Bit 24 is read in.
CODE C ST ART UP, MODE S, AND T RANSIT IONS
Reset and Power Down
T he AD1849K Stereo Codec can be reset by either of two
closely related digital input signals,
RESET
and Power Down
(PDN).
RESET
is active LO and PDN is active HI. Asserting
PDN is equivalent to asserting
RESET
with two exceptions.
First, if PDN is asserted (when
RESET
is HI), then the T SIN
and T SOUT chaining pins remain active. T SOUT will
immediately echo whatever signal is applied to T SIN during
power down. T his feature allows a very simple system test to
detect “l(fā)ife” even in a power-down state. It also allows the user
to selectively shut off Codecs in a daisy chain by powering down
the unwanted Codecs. T he down-stream Codecs will simply
move up a word position in frame. T he second difference is that
power consumption will be lower in power-down mode than in
exclusive reset mode. T he CMOUT and LOUT 1C pins will not
supply current while the AD1849K is in the power-down state
since all outputs collapse to ground.
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