參數(shù)資料
型號(hào)： AD1849KP
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Serial-Port 16-Bit SoundPort Stereo Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 16/28頁
文件大?。?/td> 293K
代理商： AD1849KP
AD1849K
REV. 0
–16–
Control Register Defaults
Upon coming out of
RESET
or Power Down, internal control registers will be initialized to the following values:
Defaults Calming Out of
RESET
or Power Down
MB
OLB
0
0
Mic Input Applied to +20 dB Fixed Gain Block
Full-Scale Line 0 Output 2.8 V p-p, Full-Scale Line 1 Output 4.0 V p-p, Full-Scale Mono Speaker
Output 8.0 V p-p
Data/Control Bit HI
Autocalibration Disabled
8 or 5.5125 kHz
Monophonic Mode
8-Bit
μ
-Law Data
FSYNC, SDT X and SCLK T hree-State within 3 SCLK Cycles after D/
C
Goes LO
Serial Bit Clock [SCLK ] is the Master Clock
256 Bits per Frame
Slave Mode
T hree-State Serial Data Output
Loopback Disabled
Digital Loopback
“1”s, i.e., T hree-State for the Open Collector Outputs
Mute Line 0 and Line 1 Outputs
Mute Left DAC
ADC Data Invalid, Autocalibration in Progress
Mute Mono Speaker
Mute Right DAC
No Overrange
Line-Level Stereo Inputs
No Gain on Left Channel
No Mix
No Gain on Right Channel
DCB
AC
DFR2:0
ST
DF1:0
IT S
MCK 2:0
FSEL1:0
MS
T X DIS
ENL
ADL
PIO1:0
OM1:0
LO5:0
ADI
SM
RO5:0
OVR
IS
LG3:0
MA3:0
RG3:0
1
0
0
0
1
0
0
2
0
1
0
0
3
0
63
1
0
63
0
0
0
15
0
Also, when making a transition from Control Mode to Data Mode, those control register values that are
not
changeable in Control
Mode get reset to the defaults above (except PIO). T he control registers that
can
be changed in Control Mode will have the values
they were just assigned. T he subset of the above list of control registers that are assigned default values on the transition from
Control Mode to Data Mode are:
Defaults at a Control-to-Data Mode Transition
OM1:0
LO5:0
SM
RO5:0
OVR
IS
LG3:0
MA3:0
RG3:0
0
63
0
63
0
0
0
15
0
Mute Line 0 and Line 1
Mute Left DAC
Mute Mono Speaker
Mute Right DAC
No Overrange
Line-Level Stereo Inputs
No Gain
No Mix
No Gain
Note that all these defaults can be changed with control information in the first Data Word. Note also that the PIO bits in the output
serial streams
always
reflect the values most recently read from the external PIO pins. (See “Parallel I/O Bits” below for timing
details.) A Control-to-Data Mode transition is no exception.
An important consequence of these defaults is that
the AD1849K Codec always comes out of reset or power down in slave mode with an
externally supplied serial bit clock (SCLK) as the clock source.
An external device
must
supply the serial bit clock and the chaining word
input signal (T SIN) initially. (See “Codec Startup, Modes, and T ransitions” below for more details.)
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相關(guān)代理商/技術(shù)參數(shù)
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AD1849KP-REEL 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 44-Pin PLCC T/R
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