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參數(shù)資料
| 型號： | AD1849KP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Serial-Port 16-Bit SoundPort Stereo Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 293K |
| 代理商： | AD1849KP |
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AD1849K
REV. 0
–10–
T he loopback modes are shown graphically in Figure 3.
GAIN
MONITOR
DISABLE
Σ
AD1849K
LINE, MIC
INPUT
DISCONNECTED
FUNCTIONAL
SDTX
SDRX
0
1
LINE 0
OUTPUT
LINE 1
A/D
μ/A-LAW
ENCODE
μ/A-LAW
DECODE
D/A
MUTE
AD1849K Analog Loopback D-A-D
GAIN
MONITOR
Σ
AD1849K
LINE, MIC
INPUT
SDTX
SDRX
LINE 0,
LINE 1
OUTPUT
FUNCTIONAL
A/D
μ/A-LAW
ENCODE
μ/A-LAW
DECODE
D/A
MUTE
AD1849K Digital Loopback D-D
Figure 3. AD1849K Loopback Modes
Clocks and Sample Rates
T he AD1849K can operate from external crystals, from a 256
×
F
S
input clock, from an input clock with a programmable divide
factor, or from the serial port’s bit clock (at 256
×
F
S
), selected
under software control. T wo crystal inputs are provided to
generate a wide range of sample rates. T he oscillators for these
crystals are on the AD1849K , as is a multiplexer for selecting
between them. T hey can be overdriven with external clocks by
the user, if so desired. T he recommended crystal frequencies are
16.9344 MHz and 24.576 MHz. From them the following sample
rates can be internally generated: 5.5125, 6.615, 8, 9.6, 11.025,
16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48kHz.
Regardless of clock input source, a clock output of 256
×
F
S
is
generated (with some skew). If an external input clock or the
serial port’s bit clocks are selected to drive the AD1849K ’s
internal operation, they should be low jitter clocks. If no
external clock will be used, Analog Devices recommends tying
the clock input pin (CLK IN) to ground. If either external
crystal is not used, Analog Devices recommends tying its input
(CIN1 and/or CIN2) to ground.
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