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參數(shù)資料
| 型號： | AD1849KP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Serial-Port 16-Bit SoundPort Stereo Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 293K |
| 代理商： | AD1849KP |
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AD1849K
REV. 0
–12–
Control Byte 2, Data Format Register
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
0
0
DF R2
DF R1
DF R0
ST
DF 1
DF 0
55
54
53
52
51
50
49
48
DFR2:0
Data conversion frequency (F
S
) select tin kHz):
DFR
Divide Factor
0
3072
1
1536
2
896
3
768
4
448
5
384
6
512
7
2560
Note that the AD1849K ’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an
external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin
(COUT 1 or COUT 2) should be left unconnected. T he external clock source need not be at the recommended crystal
frequencies, and it will be divided down by the selected Divide Factor.
Global stereo mode. Both converters are placed in the same mode.
0
Mono mode. T he left analog input appears at both ADC outputs. T he left digital input appears at both DAC outputs.
1
Stereo mode
Codec data format selection:
0
16-bit twos-complement PCM linear
1
8-bit
μ
-law companded
2
8-bit A-law companded
3
8-bit unsigned PCM linear
X T AL1 (24.576 MHz)
8
16
27.42857
32
N/A
N/A
48
9.6
X T AL2 (16.9344 MHz)
5.5125
11.025
18.9
22.05
37.8
44.1
33.075
6.615
ST
DF1:0
Control Byte 3, Serial Port Control Register
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
IT S
MCK 2
MCK 1
MCK 0
FSEL 1
FSEL 0
MS
T X DIS
47
46
45
44
43
42
41
40
IT S
Immediate three-state:
0
FSYNC, SDT X and SCLK three-state within 3 SCLK cycles after D/
C
goes LO
1
FSYNC, SDT X and SCLK three-state immediately after D/
C
goes LO
Clock source select for Codec internal operation:
0
Serial bit clock (SCLK ) is the master clock at 256
×
F
S
1
24.576 MHz crystal (X T AL1) is the clock source
2
16.9344 MHz crystal (X T AL2) is the clock source
3
External clock (CLK IN) is the clock source at 256
×
F
S
4
External clock (CLK IN) is the clock source, divided by the factor selected by DFR2:0
(External clock must be stable and valid within 2000 periods after it is selected.)
Frame size select:
0
64 bits per frame
1
128 bits per frame
2
256 bits per frame
3
Reserved
Note that FSEL is overridden in Data Mode when SCLK is the clock source (MCK = “0”). When SCLK is
providing the 256
×
F
S
clock for internal Codec operation, 256 bits per frame is effectively selected, regardless of
FSEL’s contents.
Master/slave mode for the serial interface:
0
Receive serial clock (SCLK ) and T SIN from an external device (“slave mode”)
1
T ransmit serial clock (SCLK ) and frame sync (FSYNC) to external devices (“master mode”)
Note that MS is overridden when SCLK is the clock source (MCK = “0”). When SCLK is providing the clock for
internal Codec operation, slave mode is effectively selected, regardless of the contents of MS
.
T ransmitter disable:
0
Enable serial output
1
T hree-state serial data output (high impedance)
Note that Control Mode overrides T X DIS. In Control Mode, the serial output is always enabled.
MCK 2:0
FSEL1:0
MS
T X DIS
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