參數(shù)資料
型號(hào)： AD1815
廠商： Analog Devices, Inc.
英文描述： SoundComm Controller(SoundComm 控制器)
中文描述： SoundComm控制器（SoundComm控制器）
文件頁數(shù)： 32/44頁
文件大?。?/td> 426K
代理商： AD1815
AD1815
–32–
REV. 0
Table VIII. Sound System Indirect Registers
(High Byte)
5
(Low Byte)
4
LBT D [7:0]
ADDRESS
00 (0x00)
01 (0x01)
02 (0x02)
03 (0x03)
04 (0x04)
05 (0x05)
06 (0x06)
07 (0x07)
08 (0x08)
09 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
32 (0x20)
33 (0x21)
34 (0x22)
35 (0x23)
36 (0x24)
37 (0x25)
38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29 )
42 (0x2A)
43 (0x2B)
44 (0x2C)
45 (0x2D)
46 (0x2E)
7
6
4
3
2
1
0
7
6
5
3
2
1
0
RES
PIE
C IE
T IE
VIE
VPSR [15.8]
VCSR [15:8]
D IE
RIE
JIE
SIE
RES
X C 1
X C 0
VPSR [7:0]
VCSR [7:0]
L VM
L FMM
L S1M
L S0M
RES
RES
RES
RES
LVA [5:0]
LFMA [5:0]
LS1A [5:0]
LS0A [5:0]
RVM
L FMM
RS1M
RS0M
RES
RES
RES
RES
RVA [5:0]
RFMA [5:0]
RS1A [5:0]
RS0A [5:0]
PBC [15:8]
PCC [15:8]
CBC [15:8]
CCC [15:8]
T BC [15:8]
T CC [15:8]
PBC [7:0]
PCC [7:0]
CBC [7:0]
CCC [7:0]
T BC [7:0]
T CC [7:0]
L MVM
L C D M
L SY M
L VDM
L L M
MC M
L AGC
WSE
DS1
RES
RES
RES
RES
RES
LMVA [4:0]
LCDA [4:0]
LSYA [4:0]
LVDA [4:0]
LLA [4:0]
MCA [4:0]
LAG [3:0]
RES
ADR
RMVM
RC DM
RSY M
RVDM
RL M
M M
RAGC
RES
RES
RES
RES
RES
RES
RMVA [4:0]
RCDA [4:0]
RSYA [4:0]
RVDA [4:0]
RLA [4:0]
MA [4:0]
RAG [3:0]
I2SF1 [1:0]
I01
FMSR [7:0]
S1SR [7:0]
S0SR [7:0]
MSR [7:0]
PCR [7:0]
M20
RES
LAS [2:0]
RES
DIT
RAS [2:0]
C D E
DS0
C NP
D M E
FSMR [15:8]
S1SR [15:8]
S0SR [15:8]
MSR [15:8]
PCR [15:8]
IME
I1T
IMR
I0T
COF [3:0]
PBI
I2SF0 [1:0]
DFS [2:0]
D MR
C PI
FMI
I1I
M D M
MMM
RES
RES
MDA [4:0]
MMA [4:0]
RES
MAG [3:0]
RES
RES
VMU
VUP
VDN
BM [4:0]
MB0R [15:8]
MB1R [15:8]
PIR
VER [15:8]
RES
MB0R [7:0]
MB1R [7:0]
RES
VER [7:0]
RES
C PD
RES
PIW
PAA
PDA
PD P
PT B
[00] INDIRECT LOW BYTE TMP
7
6
5
DEFAULT = [0xXX]
2
1
4
3
2
1
0
7
6
5
4
3
0
RES
LBT D [7:0]
LBT D [7:0] Low Byte T emporary Data holding latch for register pair writes
Written on any write to [SSBase + 2]
Read from [SSBase + 2] when the indirect address is 0x00
[01] INTERRUPT ENABLE AND EXTERNAL CONTROL
7
6
5
4
PIE
C IE
T IE
VIE
DEFAULT = [0x0102]
2
1
X C 1
3
2
1
0
7
6
5
4
3
0
D IE
RIE
JIE
SIE
RES
X C 0
X C0
(R/W)
External Control 0. T he state of this bit is reflected on the X CT LO pin. T his pin is also muxed with
PCLK O. COF must be greater than 11 for PCLK O to be disabled, SS [32].
X C1
(R/W)
External Control 1. T he state of this bit is reflected on the X CT L1 pin. X CT L1 may also be used for
Ring-In Interrupt.
Sound Blaster Interrupt Enable;
0
Sound Blaster Interrupt disabled
1
Sound Blaster Interrupt enabled
Joystick Interrupt Enable;
0
Joystick Interrupt disabled
1
Joystick Interrupt enabled
SIE
(R/W)
JIE
(R/W)
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