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參數(shù)資料
| 型號(hào)： | AD1815 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SoundComm Controller(SoundComm 控制器) |
| 中文描述： | SoundComm控制器（SoundComm控制器） |
| 文件頁數(shù)： | 25/44頁 |
| 文件大?。?/td> | 426K |
| 代理商： | AD1815 |
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AD1815
–25–
REV. 0
[Base+0]
Chip/Modem Status/Indirect Address
7
6
5
4
3
2
1
0
CRDY
IMRDY
INADR[5:0]
RESET = [0x00]
INADR [5:0] (RW) Indirect Address for Sound System (SS). T hese bits are used to access the Indirect Registers shown in T able VIII.
All registers data must be written in pairs, low byte followed by high byte, by loading the Indirect SS Data
Registers, (Base +2) and (Base +3).
IMRDY
(RO) ISA Modem Ready. T he AD1815 asserts this bit when the modem can accept data.
0
Modem not ready.
1
Modem ready.
CRDY
(RO) AD1815 Ready. T he AD1815 asserts this bit when AD1815 can accept data.
0
AD1815 not ready.
1
AD1815 ready.
[Base+1]
Interrupt Status
7
PI
6
5
4
3
2
1
0
SI
C I
T I
VI
DI
RI
GI
RESET = [0x00]
SI
(RO) SoundBlaster generated Interrupt.
0
No interrupt.
1
SoundBlaster interrupt pending.
(RW) Game Interrupt (Sticky, Write “0” to Clear).
0
No interrupt.
1
An interrupt is pending due to Digital Game Port data ready.
(RW) Ring Interrupt (Sticky, Write “0” to Clear).
0
No interrupt.
1
An interrupt is pending due to a Hardware Ring pin being asserted.
(RW) DSP Interrupt (Sticky, Write “0” to Clear).
0
No interrupt.
1
An interrupt is pending due to a write to the DIT bit in indirect register [33] bit <13>.
(RW) Volume Interrupt (Sticky, Write “0” to Clear).
0
No interrupt.
1
An interrupt is pending due to Hardware Volume Button being pressed.
(RW) T imer Interrupt. T his bit indicates there is an interrupt pending from the timer count registers. (Sticky,
Write “0” to Clear).
0
No interrupt.
1
Interrupt is pending from the timer count register.
(RW) Capture Interrupt. T his bit indicates that there is an interrupt pending from the capture DMA count register.
(Sticky, Write “0” to Clear).
0
No interrupt.
1
Interrupt is pending from the capture DMA count register.
(RW) Playback Interrupt. T his bit indicates that there is an interrupt pending from the playback DMA count
register. (Sticky, Write “0” to Clear).
0
No interrupt.
1
Interrupt is pending from the playback DMA count register.
GI
RI
DI
VI
T I
CI
PI
[Base+2]
Indirect SS Data Low Byte
7
6
5
4
3
2
1
0
Indirect SS Data [7:0]
RESET = [0xX X ]
[Base+3]
Indirect SS Data High Byte
7
6
5
4
3
2
1
0
Indirect SS Data [15:8]
RESET = [0xX X ]
Indirect SS
Data [15:0]
Indirect Sound System Data. Data in this register is written to the Sound System Indirect Register specified by the
address contained in INDAR [5:0], Sound System Direct Register [Base +0]. Data is written when the Indirect SS
Data High Byte value is loaded.
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| AD1816AJS | SoundPort Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1815JS | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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| AD1816AJS | 制造商:AD 制造商全稱:Analog Devices 功能描述:SoundPort Controller |
| ad1816ajs-eeprom | 制造商:Rochester Electronics LLC 功能描述:AD1816A SOUND PORT CONTRO - Bulk 制造商:Analog Devices 功能描述: |
| AD1816AJST | 制造商:AD 制造商全稱:Analog Devices 功能描述:SoundPort Controller |
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