參數(shù)資料
型號(hào)： AD1815
廠商： Analog Devices, Inc.
英文描述： SoundComm Controller(SoundComm 控制器)
中文描述： SoundComm控制器（SoundComm控制器）
文件頁(yè)數(shù)： 19/44頁(yè)
文件大小： 426K
代理商： AD1815
AD1815
–19–
REV. 0
Table I. Modem Disabled Time Slot Map
Time Slot
SDI Pin
SDO Pin
0
1
2
3
4
5
6
7
8
9
10
11
Control Word Input
Control Register Data Input
* SS/SB ADC Right Input (to ISA)
* SS/SB ADC Left Input (to ISA)
* SS/SB DAC Right Input (to Codec) SS/SB DAC Right Output (from ISA)
* SS/SB DAC Left Input (to Codec)
* FM DAC Right Input (to Codec)
* FM DAC Left Input (to Codec)
* I
2
S 1 DAC Right Input (to Codec)
* I
2
S 1 DAC Left Input (to Codec)
* I
2
S 0 DAC Right Input (to Codec)
* I
2
S 0 DAC Left Input (to Codec)
Status Word Output
Control Register Data Output
SS/SB ADC Right Output (from Codec)
SS/SB ADC Left Output (from Codec)
SS/SB DAC Left Output (from ISA)
FM DAC Right Output (from FM Synth Block)
FM DAC Left Output (from FM Synth Block)
I
2
S 1 DAC Right Output (from I
2
S Port 1)
I
2
S 1 DAC Left Output (from I
2
S Port 1)
I
2
S 0 DAC Right Output (from I
2
S Port 0)
I
2
S 0 DAC Left Output (from I
2
S Port 0)
*T his data is ignored by the AD1815 unless the channel pair is in intercept mode (see below).
SS - Sound System Mode
SB = Sound Blaster Mode
When the modem channel is enabled (DSP modem mode), time slots are mapped as above except for time Slot 2, which is as
follows:
2
Modem DAC Input (to Codec)
When the modem channel is enabled, stereo SB or SS capture is not possible and SB and SS fall back to mono capture. T he right
capture channel then gets the left channel capture data.
At startup (after pin reset), there are exactly 12 time slots per frame. T he frame rate will be 57,291 and 2/3 Hz (11MHz sclk/
(16 bits
×
12 slots)). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot per
frame mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical.
T he frame rate can be changed from its default by a write to the DFS(2:0) bits in register 33. Rate choices are: Maximum (57,291
and 2/3 Hz default), Modem rate, SS capture rate, SS playback rate, FM rate, I
2
S Port (1) rate, or I
2
S Port (0) rate. When the frame
rate is less than 57,261 and 2/3 Hz, extra SCLK periods are added to fill up the time. T he number of SCLK periods added will vary
somewhat from frame to frame.
Similar to the AD1843, Valid out, Request in, and Valid in bits located in the control and status words are used to control sample
data flow. If a channel’s sample rate is equal to the frame rate, these bits can be ignored since they will predictably always be 1s.
By default, the DSP serial port only allows codec sample data I/O to be monitored. Intercept modes must be enabled to make substi-
tutions in sample data flow to and from the codec. T here are five bits in SS register 33 which enable intercept mode for SS capture,
SS playback, FM playback, I
2
S Port (1) playback, and I
2
S Port (0) playback.
Modem ADC Output (from Codec)
Control Word Input (Slot 0 SDI)
15
14
RES
6
R/W
13
12
11
10
9
8
FCL R
7
AL IVE
MODVI
5
SSCVI
4
SSPVI
3
IA[5:0]
FMVI
2
IS1VI
1
IS0VI
0
IA [5:0]
Indirect Register Address. Sound System Indirect Register Address defines the address of indirect registers shown
in T able VI.
Read/Write request. Either a read from or a write to a SS indirect register occurs every frame. Setting this bit ini-
tiates a SS indirect register read while clearing this bit initiates a SS indirect register write.
DSP port alive bit. When set, this bit indicates to the powerdown timer that the DSP port is active. When cleared,
this bit indicates that the DSP port is inactive.
I
2
S Port 0 Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for the I
2
S
port 0 channel pair, or (2) T he AD1815 did not request data from the I
2
S port 0 channel pair in the previous
frame. Otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left I
2
S Port 0 substitution
data. When this bit is cleared, data in slots 10 and 11 is ignored.
I
2
S Port 1 Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for I
2
S port
1 channel pair, or (2) T he AD1815 did not request data from the I
2
S port channel pair in the previous frame. Oth-
erwise, setting this bit indicates that Slots 8 and 9 contain valid right and left I
2
S Port 1 substitution data. When
this bit is cleared, data in slots 8 and 9 is ignored.
R/W
ALIVE
IS0VI
IS1VI
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