參數(shù)資料
型號(hào)： AD1815
廠商： Analog Devices, Inc.
英文描述： SoundComm Controller(SoundComm 控制器)
中文描述： SoundComm控制器（SoundComm控制器）
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 426K
代理商： AD1815
AD1815
–20–
REV. 0
FMVI
FM Synthesis Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for the
FM synthesis channel pair, or (2) T he AD1815 did not request data from the FM synthesis channel pair in the
previous frame (see the FMRQ Bit 9 in the status word output). Otherwise, setting this bit to 1 indicates that slots
6 and 7 contain valid right and left FM synthesis channel substitution data. When this bit is reset to 0, data in slots
6 and 7 is ignored.
SS/SB Playback Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for
SS/SB playback, or (2) T he AD1815 did not request data for SS/SB playback in the previous frame (see the
SSPRQ bit in the Status Word Output). Otherwise, setting this bit indicates that Slots 4 and 5 contain valid right
and left SS/SB playback substitution data. If in “capture rate equal to playback rate” mode, setting this bit also in-
dicates that valid capture substitution data is being sent to the AD1815. If not in modem mode, right and left
channel capture substitution data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture
substitution data is accepted in slots 2 and 3. When this bit is cleared, data in all slots controlled by this bit, as de-
fined above, is ignored.
SS/SB Capture Substitution Data Input Valid Flag. T his bit is ignored if: (1) Intercept mode is not enabled for SS/
SB capture, or (2) T he AD1815 did not request data for SS/SB capture in the previous frame (see the SSCRQ bit
in the Status Word Output). Otherwise, setting this bit indicates that valid SS/SB capture substitution data is being
sent to the AD1815. If not in modem mode, or DSP port or ISA bus based, right and left channel capture data is
accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture substitution data is accepted in Slot
3, because Slot 2, which is mapped to the right capture channel, is being used for modem. T his mono data will,
however, be sent to both left and right ISA SS/SB capture channels. When this bit is cleared, data in Slots 3 and 2
is ignored.
Modem Input Valid flag. T his bit is ignored if: (1) T he AD1815 is in DSP modem mode, or (2) If the AD1815
did not request data for the modem in the previous frame (see the MODRQ bit in the Status Word Output). When
in DSP modem mode, setting this bit indicates that Slot 2 contains valid modem data to be transmitted. When this
bit is cleared, data in Slot 2 is ignored.
Reserved: T o insure future compatibility write “0” to all reserved bits.
DSP Port Clear Status Flag. When you set this bit, (write 1), the PNPR and PDN flag bits in the status word (Bits
15 and 14 of slots 0 SDO) are cleared. When you clear this bit, (writing a 0), it has no effect on PNPR and PDN
and preserves them in the previous states.
SSPVI
SSCVI
MODVI
RES
FCLR
Status Word Output (Slot 0 SDO)
15
14
13
12
11
10
9
8
PD N
7
MB1
PNPR
6
MB0
MODVO
5
MODRQ
SSCVO
4
SSCRQ
SSPVO
3
SSPRQ
FMVO
2
FMRQ
IS1VO
1
IS1RQ
IS0VO
0
IS0RQ
IS0RQ
I
2
S Port (0) Input Request Flag. T his bit is set if intercept mode is enabled for I
2
S Port (0) and its four-word ste-
reo input buffer is not full.
I
2
S Port (1) Input Request Flag. T his bit is set if intercept mode is enabled for I
2
S Port (1) and its four-word ste-
reo input buffer is not full.
FM Synthesis Input Request Flag. T his bit is set if intercept mode is enabled for FM synthesis and its four-word
stereo input buffer is not full.
SS/SB Capture Input Request Flag. T his bit is set if intercept mode is enabled for SS/SB playback and its four-
word stereo input buffer is not full.
SS/SB Capture Input Request Flag. T his bit is set if intercept mode is enabled for SS/SB capture and its
four-word stereo input buffer is not full.
Modem Input Request Flag. T his bit is set if the modem is enabled and its four-word stereo input buffer is not full.
Mailbox 0 Status Flag. T his bit is set if the most recent action to SS indirect register 42 (DSP port Mail Box 1)
was a write, and is cleared if the most recent action was a read. T he status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
Mailbox 1 Status Flag. T his bit is set if the most recent action to SS indirect register 43 (DSP port Mail Box 1)
was a write and is cleared if the most recent action was a read. T he status of this bit is also reflected in SS indirect
register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a
host CPU on the ISA bus.
I
2
S Port 0 Valid Out. T his bit is set if Slots 10 and 11 contain valid right and left I
2
S Port 0 data.
I
2
S Port 1 Valid Out. T his bit is set if Slots 8 and 9 contain valid right and left I
2
S Port 1 data.
IS1RQ
FMRQ
SSPRQ
SSCRQ
MODRQ
MB0
MB1
IS0VO
IS1V1
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